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PDF ML6510 Data sheet ( Hoja de datos )
| Número de pieza | ML6510 | |
| Descripción | Series Programmable Adaptive Clock Manager (PACMan) | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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March 1997
ML6510*
Series Programmable Adaptive
Clock Manager (PACMan™)
GENERAL DESCRIPTION
The ML6510 (Super PACMan™) is a Programmable
Adaptive Clock Manager which offers an ideal solution for
managing high speed synchronous clock distribution in
next generation, high speed personal computer and
workstation system designs. It provides eight channels of
deskew buffers that adaptively compensate for clock skew
using only a single trace. The input clock can be either
TTL or PECL, selected by a bit in the control register.
Frequency multiplication or division is possible using the
M&N divider ratio, within the maximum frequency limit.
0.5X, 1X, 2X and 4X clocks can be easily realized.
The ML6510 is implemented using a low jitter PLL with
on-chip loop filter. The ML6510 deskew buffers adaptively
compensate for clock skew on PC boards. An internal
skew sense circuit is used to sense the skew caused by the
PCB trace and load delays. The sensing is done by
detecting a reflection from the load and the skew is
corrected adaptively via a unique phase control delay
circuit to provide low load-to-load skew, at the end of the
PCB traces. Additionally, the ML6510 supports PECL
reference clock outputs for use in the generation of clock
trees with minimal part-to-part skew. The chip configuration
can be programmed to generate the desired output
frequency using the internal ROM or an external serial
EEPROM or a standard two-wire serial microprocessor
interface.
FEATURES
s Input clocks can be either TTL or PECL with low
input to output clock phase error
s 8 independent, automatically deskewed clock
outputs with up to 5ns of on-board deskew range
(10ns round trip)
s Controlled edge rate TTL-compatible CMOS clock
outputs capable of driving 40Ω PCB traces
s 10 to 80MHz (6510-80) or 10 to 130MHz (6510-130)
input and output clock frequency range
s Less than 500ps skew between inputs at the
device loads
s Small-swing reference clock outputs for minimizing
part-to-part skew
s Frequency multiplication or division is possible using
the M&N divider ratio
s Lock output indicates PLL and deskew buffer lock
s Test mode operation allows PLL and deskew buffer
bypass for board debug
s Supports industry standard processors like Pentium™,
Mips, SPARC™, PowerPC,™ Alpha™, etc.
*Some Packages Are Obsolete
SYSTEM BLOCK DIAGRAM
CLOCK IN
CLOCK SUBSYSTEM
ML6510
•
8•
•
CPU
CLK
LOCAL BUS
CACHE
CONTROLLER
CACHE
RAM
MEMORY BUS
CONTROLLER
CLOCK OUT TO
COMPONENTS
MEMORY BUS
1
1 page  
ML6510
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section).
tR
tF
fIN
fOUT
Rise time, LOAD [0-7] output
Fall time, LOAD [0-7] output
Input frequency, CLKIN pin
Output frequency , CLK [0-7]
output
0.8 → 2.0V, 80MHz
2.0 → 0.8V, 80MHz
ML6510-80
ML6510-130 (Note 2)
150
150
10
10
10
1500
1500
80
80
130
ps
ps
MHz
MHz
MHz
fVCO
DC
PLL VCO operating frequency
Output duty cycle
Measured at device load, at 1.5V
80
40
160 MHz
60 %
tJITTER
Output jitter
Cycle-to-cycle
Peak-to-peak
75 ps
150 ps
tLOCK
PLL and deskew lock time
After programming is complete
11 ms
SKEW CHARACTERISTICS All skew measurements are made at the load, at 1.5V threshold each output load can vary independently
within the specified range for a generic load (see Load Conditions section).
tSKEWR
Output to output rising
edge skew, all clocks
500 ps
tSKEWF
Output to output
falling edge skew
Output clock frequency ≥ 50MHz
1.5 ns
tSKEWIO
CLKIN input to any
LOAD [0-7] output
rising edge skew
N=M=0
N ≥ 2, M ≥ 2
600 ps
1.25 ns
tRANGE
tSKEWB
Round trip delay CLKX to FBX
pin; output CLK period = tCLK
Output-to-output rising
edge skew, between matched
loads
Output frequency < 50MHz
Output frequency ≥ 50MHz
Providing first (see LOAD
conditions) order matching
order matching between outputs
0 10 ns
0 tCLK/2
250 ps
PART-TO-PART SKEW CHARACTERISTICS Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock
input pins of another ML6510.
tPP1 Total load-to-load skew between Slave chip CS = 1, CM = 1 and
multiple chips interfaced with
N = 0, M = 0; RCLK outputs to
reference clock pins.
CLKIN inputs distance less than 2"
tPP2 Total load-to-load skew between Slave chip CS = 1, CM = 1 and
multiple chips interfaced with
N ≥ 2, M ≥ 2; RCLK outputs to
reference clock pins.
CLKIN inputs distance less than 2"
PROGRAMMING TIMING CHARACTERISTICS
1 ns
1 ns
tRESET RESET assertion pulse
width
50 ns
tA1 AUX mode MCLK high time
tA2 AUX mode MCLK low time
tA3 AUX mode MDOUT data
hold time
2000
2000
10
ns
ns
ns
tA4 AUX mode MDOUT data
setup time
10 ns
tA5 AUX mode MCLK period
5000
ns
5
5 Page 
ML6510-80
GENERIC
LOAD
FBX
CLKX
PCB trace impedance
R1 Z0 = 40Ω to 65Ω
LOAD Lumped
CL ≤ 20pF
One way trip delay < tRANGE/2
FBX
CLKX
R1
ML6510-80
FIRST-ORDER
MATCHED LOADS
FBY
CLKY
R1
PCB trace impedance
Z0 = 40Ω to 65Ω
Length LX
LOAD Lumped
CLX ≤ 20pF
PCB trace impedance
Z0 = 40Ω to 65Ω
Length LY
|CLX – CLY| < 5pF
|LX – LY| < 4"
ZOX = ZOY
LOAD Lumped
CLY ≤ 20pF
One way trip delay < tRANGE/2
ML6510
ML6510-130
GENERIC
LOAD FBX
CLKX
R2
PCB trace impedance
Z0 = 40Ω to 65Ω
LOAD
Lumped
CL ≤ 20pF
R3
One way trip delay < tRANGE/2
FBX
CLKX
R2
PCB trace impedance
Z0 = 40Ω to 65Ω
LOAD Lumped
CLX ≤ 20pF
ML6510-130
Length LX
R3
FIRST-ORDER
MATCHED LOADS
|CLX – CLY| < 5pF
|LX – LY| < 4"
ZOX = ZOY
FBY
CLKY
R2
PCB trace impedance
Z0 = 40Ω to 65Ω
LOAD Lumped
CLY ≤ 20pF
Length LY
R3
One way trip delay < tRANGE/2
EXTERNAL INPUT CLOCKS
The external input clock to the ML6510 can be either a
differential Pseudo-ECL clock or a single-ended TTL clock.
This is selected using the CS bit in the serial shift register.
For the single-ended TTL clock tie the CLKINH and CLKINL
pins together. The ML6510 ensures that there is a well-
defined phase difference between the input and output
clocks.
RESET AND LOCK
When RESET is de-asserted, the internal programming
logic will become active, loading in the configuration bits
(see Programming the ML6510). Once the configuration is
loaded, the PLL will lock onto the reference signal, and
then the deskew blocks will adapt to the load conditions.
When all eight output clocks are stable and deskewed,
LOCK will be asserted. The asserted polarity of lock is
high. Thus, LOCK can be used to indicate that the system
is ready, or it can be used to drive the RESET input of
another PACMan in a clock tree.
5V
CHIP
VCC 0
RESET
tRESET
LOCK
tLOCK
PROGRAM IN THE
CONFIGURATION
tLOCK
PROGRAM IN THE
CONFIGURATION
RESET may be reasserted at any time to reset the chip
operations. Following a RESET assertion of valid pulse
width (see Programming Electrical Characteristics), the
ML6510 must again be loaded with a configuration, then
it will re-lock and reassert lock when all eight clock
outputs are stable and deskewed.
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ML6510.PDF ] | |
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