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PDF ML4824CP-1 Data sheet ( Hoja de datos )
| Número de pieza | ML4824CP-1 | |
| Descripción | Power Factor Correction and PWM Controller Combo | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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December 2000
ML4824
Power Factor Correction and PWM Controller Combo
GENERAL DESCRIPTION
FEATURES
The ML4824 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-2-3 specification. The ML4824 includes
circuits for the implementation of a leading edge, average
current, “boost” type power factor correction and a trailing
edge, pulse width modulator (PWM).
The device is available in two versions; the ML4824-1
(fPWM = fPFC) and the ML4824-2 (fPWM = 2 x fPFC).
Doubling the switching frequency of the PWM allows the
user to design with smaller output components while
maintaining the best operating frequency for the PFC. An
over-voltage comparator shuts down the PFC section in the
event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown-
out protection. The PWM section can be operated in
current or voltage mode at up to 250kHz and includes a
duty cycle limit to prevent transformer saturation.
s Internally synchronized PFC and PWM in one IC
s Low total harmonic distortion
s Reduces ripple current in the storage capacitor between
the PFC and PWM sections
s Average current, continuous boost leading edge PFC
s Fast transconductance error amp for voltage loop
s High efficiency trailing edge PWM can be configured
for current mode or voltage mode operation
s Average line voltage compensation with brownout
control
s PFC overvoltage comparator eliminates output
“runaway” due to load removal
s Current fed gain modulator for improved noise immunity
s Overvoltage protection, UVLO, and soft start
BLOCK DIAGRAM
16
VEAO
1
IEAO
VFB
15
2.5V
IAC
2
VRMS
4
ISENSE
3
VEA
–
+
3.5kΩ IEA
+
–
GAIN
MODULATOR
3.5kΩ
POWER FACTOR CORRECTOR
OVP
+
2.7V –
+
–
–1V +
–
PFC ILIMIT
VCCZ
13.5V
13
VCC
7.5V
REFERENCE
VREF
14
SQ
RQ
SQ
PFC OUT
12
RAMP 1
7
RAMP 2
8
8V
OSCILLATOR
x2
(-2 VERSION ONLY)
DUTY CYCLE
LIMIT
RQ
VDC
6
VCC
SS
5
50µA
8V
DC ILIMIT
9
1.25V
–
+
–
+
VIN OK
VFB –
1V –
2.5V +
+
DC ILIMIT
PULSE WIDTH MODULATOR
VCCZ
SQ
RQ
PWM OUT
11
UVLO
REV. 1.01 12/7/2000
1 page  
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
Output High Voltage
PWM
Rise/Fall Time
Duty Cycle Range
Output Low Voltage
Output High Voltage
SUPPLY
Rise/Fall Time
Shunt Regulator Voltage (VCCZ)
VCCZ Load Regulation
VCCZ Total Variation
Start-up Current
Operating Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
CONDITIONS
VIEAO > 4.0V
VIEAO < 1.2V
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
ML4824-1
ML4824-2
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
25mA < ICC < 55mA
Load, Temp
VCC = 11.8V, CL = 0
VCC < VCCZ - 0.5V, CL = 0
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1.
ML4824
MIN TYP MAX UNITS
0
90 95
0.4 0.8
0.8 2.0
0.7 1.5
10 10.5
9.5 10
50
%
%
V
V
V
V
V
ns
0-44
0-37
10
9.5
0-47
0-40
0.4
0.8
0.7
10.5
10
50
0-50
0-45
0.8
2.0
1.5
%
%
V
V
V
V
V
ns
12.8
12.4
12
2.7
13.5
±100
0.7
16
13
3.0
14.2
±300
14.6
1.0
19
14
3.3
V
mV
V
mA
mA
V
V
REV. 1.01 12/7/2000
5
5 Page 
VBIAS
RBIAS
VCC
ML4824
GND
10nF
CERAMIC
1µF
CERAMIC
Figure 3. External Component Connections to VCC
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will
be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.
ML4824
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using this
method.
TYPICAL APPLICATIONS
Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.
L1
+ I1
VIN
DC
SW2 I2 I3
I4
SW1
C1
RL
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
RAMP
VEAO
VSW1
TIME
TIME
Figure 4. Typical Trailing Edge Control Scheme.
REV. 1.01 12/7/2000
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ML4824CP-1.PDF ] | |
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