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81C55 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer 81C55
Beschreibung Radiation Hardened 256 x 8 CMOS RAM
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 14 Seiten
81C55 Datasheet, Funktion
March 1996
HS-81C55RH,
HS-81C56RH
Radiation Hardened
256 x 8 CMOS RAM
Features
• Devices QML Qualified in Accordance with
MIL-PRF-38535
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 105 RAD(Si)
- Transient Upset > 1 x 108 RAD(Si)/s
- Latch-Up Free > 1 x 1012 RAD(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current 200µA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55oC to +125oC
Description
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
Functional Diagram
IO/M
AD0 - AD7
CE OR CE
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
256 x 8
STATIC
RAM
PORT A
A 8 PA0 - PA7
PORT B
B 8 PB0 - PB7
TIMER
PORT C
C 8 PC0 - PC5
VDD (10V)
GND
81C55RH = CE
81C56RH = CE
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
5962R9XXXX01QXC
5962R9XXXX01VXC
5962R9XXXX02QRC
5962R9XXXX02VRC
5962R9XXXX02QXC
5962R9XXXX02VXC
HS1-81C55RH/Sample
HS9-81C55RH/Sample
HS1-81C56RH/Sample
HS9-81C56RH/Sample
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
+25oC
SCREENING LEVEL
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
Sample
Sample
Sample
PACKAGE
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
40 Lead SBDIP
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
40 Lead SBDIP
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518056
File Number 3039.1






81C55 Datasheet, Funktion
Waveforms
READ
CE (81C55RH)
OR
CE (81C56RH)
IO/M
AD0-7
ALE
RD
Specifications HS-81C55RH, HS-81C56RH
tAD
ADDRESS
tAL tLA
DATA VALID
tLL
tRIDE
tRDF
tRD
tCL
tLC
tCC tRV
WRITE
CE (81C55RH)
OR
CE (81C56RH)
IO/M
AD0-7
ALE
WR
ADDRESS
tAL tLA
tLL tLC
DATA VALID
tDW
tCL
tWD
tCL
tCC tRV
Spec Number 518056
6

6 Page









81C55 pdf, datenblatt
HS-81C55RH, HS-81C56RH
The outputs of the HS-81C55/56RH are “glitch-free”
meaning that you can write a “1” to a bit position that was
previously “1” and the level at the output pin will not change.
Note also that the output latch is cleared when the port
enters the input mode. the output latch cannot be loaded by
writing to the port if the port is in theinput mode. The result is
that each time a port mode is changed from input to output,
the output pins will go low. When the HS-81C55/56RH is
RESET, the output latches are all cleared and all 3 ports
enter the input mode.
When in the ALT1 or ALT2 modes, the bits of Port C are
structured like the diagram above in the simple input or
output mode, respectively.
Reading from an input port with nothing connected to the
pins will provide unpredictable results.
Figure 7 shows how the HS-81C55/56RH I/O ports might be
configured in a typical system.
Timer Section
The timer is a 14 bit down counter that counts the TIMER IN
pulses and provides either a square wave or pulse when
terminal count (TC) is reached.
The timer has the I/O address XXXXX100 for the low order
byte of the register and the I/O address XXXXX101 for the
high order byte of the register. (See Figure 5).
To program the timer, the COUNT LENGTH REG is loaded
first, one byte at a time, by selecting the timer addresses.
Bits 0-13 of the high order count register will specify the
length of the next count and bits 14-15 of the high order
register will specify the timer output mode (see Figure 8).
The value loaded into the count length register can have any
value from 2H through 3FFH in Bits 0-13.
PORT A OUTPUT PORT A
TO HS-80C85RH
RST INPUT
A INTR (SIGNAL DATA RECEIVED)
A BF (SIGNALS DATA READY)
PORT C
A STB (ACKNOWL. DATA RCV’D)
B STB (LOAD PORT B LATCH)
B BF (SIGNALS BUFFER IS FULL)
TO/FROM
PERIPHERAL
INTERFACE
PORT B
B INTR (SIGNALS BUFFER
READY FOR READING)
INPUT
TO INPUT PORT
(OPTIONAL)
TO HS-80C85RH
RST INPUT
FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001
76543210
M2 M1 T13 T12 T11 T10 T9 T8
TIMER
MODE
MSB OF
CNT LENGTH
76543210
T7 T6 T5 T4 T3 T2 T1 T0
LSB OF
CNT LENGTH
FIGURE 8. TIMER FORMAT
PIN ALT1
PC0 Input Port
PC1 Input Port
PC2 Input Port
PC3 Input Port
PC4 Input Port
PC5 Input Port
TABLE 1. PORT CONTROL ASSIGNMENT
ALT2
ALT3
ALT4
Output Port A INTR (Port A Interrupt) A INTR (Port A Interrupt)
Output Port A BF (Port A Buffer Full)
A BF (Port A Buffer Full)
Output Port A STB (Port A Strobe)
A STB (Port A Strobe)
Output Port Output Port
B INTR (Port B Interrupt)
Output Port Output Port
B BF (Port B Buffer Full)
Output Port Output Port
B STB (Port B Strobe)
Spec Number 518056
12

12 Page





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