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PDF ML4803IP-1 Data sheet ( Hoja de datos )
| Número de pieza | ML4803IP-1 | |
| Descripción | 8-Pin PFC and PWM Controller Combo | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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February 1999
PRELIMINARY
ML4803
8-Pin PFC and PWM Controller Combo
GENERAL DESCRIPTION
The ML4803 is a space-saving controller for power factor
corrected, switched mode power supplies that offers very
low start-up and operating currents.
Power Factor Correction (PFC) offers the use of smaller,
lower cost bulk capacitors, reduces power line loading
and stress on the switching FETs, and results in a power
supply fully compliant to IEC1000-3-2 specifications. The
ML4803 includes circuits for the implementation of a
leading edge, average current “boost” type PFC and a
trailing edge, PWM.
The ML4803-1’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the ML4803-2 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum
operating frequency for the PFC. An overvoltage
comparator shuts down the PFC section in the event of a
sudden decrease in load. The PFC section also includes
peak current limiting for enhanced system reliability.
FEATURES
s Internally synchronized PFC and PWM in one 8-pin IC
s Patented one-pin voltage error amplifier with advanced
input current shaping technique
s Peak or average current, continuous boost, leading
edge PFC (Input Current Shaping Technology)
s High efficiency trailing-edge current mode PWM
s Low supply currents; start-up: 150µA typ., operating:
2mA typ.
s Synchronized leading and trailing edge modulation
s Reduces ripple current in the storage capacitor
between the PFC and PWM sections
s Overvoltage, UVLO, and brownout protection
s PFC VCCOVP with PFC Soft Start
BLOCK DIAGRAM
VEAO
4
7V
35µA
+ PFC OFF
COMP
–
–1
M1 M2
M7
M3
R1
7
VCC
17.5V
16.2V
C1
30pF
M4
ISENSE
3
–1V
ONE PIN ERROR AMPLIFIER
+ PFC ILIMIT
– VCC
–4
PFC/PWM UVLO
+
COMP
–
VREF
26k
VDC
5
40k
ILIMIT
6
1.2V
OSCILLATOR
PFC – 67kHz
PWM – 134kHz
DUTY CYCLE
LIMIT
– PWM COMPARATOR
COMP
+
–
COMP
+
M6
1.5V
– DC ILIMIT
+
+ VCC OVP
COMP
–
REF VREF
GND
2
PFC
CONTROL
LOGIC
SOFT START
PFC OUT
1
LEADING
EDGE PFC
TRAILING
EDGE PWM
PWM
CONTROL
LOGIC
PWM OUT
8
1
1 page  
FUNCTIONAL DESCRIPTION
The ML4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a
synchronized Pulse Width Modulation (PWM) controller. It
is distinguished from earlier combo controllers by its low
pin count, innovative input current shaping technique, and
very low start-up and operating currents. The PWM section
is dedicated to peak current mode operation. It uses
conventional trailing-edge modulation, while the PFC uses
leading-edge modulation. This patented Leading Edge/
Trailing Edge (LETE) modulation technique helps to
minimize ripple current in the PFC DC buss capacitor.
The ML4803 is offered in two versions. The ML4803-1
operates both PFC and PWM sections at 67kHz, while the
ML4803-2 operates the PWM section at twice the
frequency (134kHz) of the PFC. This allows the use of
smaller PWM magnetics and output filter components,
while minimizing switching losses in the PFC stage.
In addition to power factor correction, several protection
features have been built into the ML4803. These include
soft start, redundant PFC over-voltage protection, peak
current limiting, duty cycle limit, and under voltage
lockout (UVLO). See Figure 12 for a typical application.
DETAILED PIN DESCRIPTIONS
VEAO
This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and
is shunted by the feedback compensation network.
ISENSE
This pin ties to a resistor or current sense transformer
which senses the PFC input current. This signal should be
negative with respect to the IC ground. It internally feeds
the pulse-by-pulse current limit comparator and the
current sense feedback signal. The ILIMIT trip level is –1V.
The ISENSE feedback is internally multiplied by a gain of
four and compared against the internal programmed ramp
to set the PFC duty cycle. The intersection of the boost
inductor current downslope with the internal
programming ramp determines the boost off-time.
VDC
This pin is typically tied to the feedback opto-collector. It
is tied to the internal 5V reference through a 26kW resistor
and to GND through a 40kW resistor.
ILIMIT
This pin is tied to the primary side PWM current sense
resistor or transformer. It provides the internal pulse-by
pulse-current limit for the PWM stage (which occurs at
1.5V) and the peak current mode feedback path for the
current mode control of the PWM stage. The current ramp
February 1999
ML4803
is offset internally by 1.2V and then compared against the
opto feedback voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power
drivers capable of directly driving the gate of a power
MOSFET with peak currents up to ±1A. Both outputs are
actively held low when VCC is below the UVLO threshold
level.
VCC
VCC is the power input connection to the IC. The VCC start-
up current is 150µA . The no-load ICC current is 2mA. VCC
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the
operating frequency and the MOSFET gate charge (Qg),
average PFC and PWM output currents can be calculated
as IOUT = Qg x F. The average magnetizing current
required for any gate drive transformers must also be
included. The VCC pin is also assumed to be proportional
to the PFC output voltage. Internally it is tied to the
VCCOVP comparator (16.2V) providing redundant high-
speed over-voltage protection (OVP) of the PFC stage.
VCC also ties internally to the UVLO circuitry, enabling
the IC at 12V and disabling it at 9.1V. VCC must be
bypassed with a high quality ceramic bypass capacitor
placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
ML4803.
VCC is typically produced by an additional winding off
the boost inductor or PFC Choke, providing a voltage that
is proportional to the PFC output voltage. Since the
VCCOVP max voltage is 16.2V, an internal shunt limits
VCC overvoltage to an acceptable value. An external
clamp, such as shown in Figure 1, is desirable but not
necessary.
VCC is internally clamped to 16.7V minimum, 18.3V
maximum. This limits the maximum VCC that can be
applied to the IC while allowing a VCC which is high
VCC
1N4148
1N4148
1N5246B
GND
Figure 1. Optional VCC Clamp
5
5 Page 
ML4803
LINE F1 5A 250V
J1-1 R24
470kΩ
0.5W
NEUTRAL
J1-2 C20
4.7nF
250VAC
C19
4.7nF
250VAC
C4
0.47µF
250VAC
BR1
600V
4A
TH1
10Ω
5A
L3
R22
10kΩ
R3 0.15Ω 3W
102T
L2
1000µH
R1
CR1 8A, 600V
Q5
36Ω
R2
36Ω
CR5
16V
0.5W
Q2
C1
220µF
450V
Q4
CR7 R8 36Ω
T2
13
R30 200Ω
R38 22Ω
Q1
R23
10kΩ
C29 0.01µF
10 4
C16
0.01µF
CR3
T1
R13
5.62MΩ
C7
0.1µF
R7
10Ω
C23
0.01µF R29 20kΩ
CR16
R19
IN4148 10kΩ
R27
20kΩ
3W
R26
20kΩ
3W
CR8
C11 L2
1000µF
C22 C9
1µF 1µF 4T
R31
10Ω
C21
1µF
CR15
R4 1kΩ
CR12
7.0V
R25
390kΩ
C8
0.15µF
R12
5.62MΩ
R28
20kΩ
1
2
3
4
C15
0.015µF
C5
8.2nF
ML4803
8
PFC PWM
GND
ISENSE
VEAO
VCC
ILIMIT
VDC
7
6
5
C28
C6 1µF C27
1µF 0.01µF
CR10
R5 36Ω
Q3
5
R11 150Ω
R32 100Ω
4
CR11
C10
2.2nF
CR9 R21
10kΩ
R10
0.75Ω
3W
CR4
R20
510Ω
CR18 51V
C18 4.7nF R36 220Ω
CR2 CR2
30A 30A, 60V
60V
C2
2200µF
L1 25µH
C25
0.01µF
500V
12V
J2-1
C3 R14
1µF 150Ω
2W
12VRET
J2-2
C26
0.01µF
500V
R6 1.2kΩ
R9
1.5kΩ
C14
4.7µF
U3
1
2
R37
330Ω
C17
0.1µF
C13 1nF
R15
9.09kΩ
R17 3.3kΩ
3
U2
2
1
C12 0.1µF R18 1kΩ
R16
2.37kΩ
Figure 12. Typical Application Circuit. Universal Input 240W 12V DC Output
February 1999
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ML4803IP-1.PDF ] | |
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