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PDF ML4802IS Data sheet ( Hoja de datos )
| Número de pieza | ML4802IS | |
| Descripción | PFC/PWM Controller Combo with Green Mode | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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December 2000
PRELIMINARY
ML4802
PFC/PWM Controller Combo with Green Mode
GENERAL DESCRIPTION
The ML 4802 is a controller for power factor corrected,
switched mode power supplies that offers Green Mode
operation and reduced start-up and operating currents.
Green Mode is an efficiency improving circuit feature
which operates automatically in low power situations.
This feature helps meet the demands of Energy Star™
programs.
Power Factor Correction (PFC) offers the use of lower cost
bulk capacitors, reduces power line loading and stress on
the switching FETs. The ML4802 includes circuits for the
implementation of a leading edge, average current,
“boost” type power factor corrector and a trailing edge
Pulse Width Modulator (PWM).
The PFC frequency of the ML4802 is automatically
synchronized to be one half that of the PWM. This
technique allows the user to design with smaller PWM
components while maintaining the optimum operating
frequency for the PFC. An over-voltage comparator shuts
down the PFC section in the event of a sudden decrease
in load. The PFC section also includes peak current
limiting and brown-out protection.
FEATURES
s Internally synchronized PFC and PWM in one IC
s Green Mode maximizes efficiency during low power
standby operation
s Low supply current
(Start-up 200µA typ., operating 5.5mA typ.)
s Average current continuous boost leading edge PFC
s High efficiency trailing edge PWM can be configured
for current mode operation
s Reduced ripple current in the storage capacitor
between the PFC and PWM sections
s PFC overvoltage comparator eliminates output
“runaway” due to load removal
s Current fed gain modulator for improved noise
immunity
s Overvoltage protection, UVLO, and soft start
BLOCK DIAGRAM
VEAO
16
IEAO
1
VFB 15
2.5V
IAC 2
VRMS 4
ISENSE 3
VEA
-
+
1.8kΩ
IEA
+
–
GAIN
MODULATOR
8V
1.8kΩ
POWER FACTOR CORRECTOR
2.75V
+
- OVP
PFC
CONTROLLER
-1V +
-
PFC ILIMIT
VCC
13
7.5V
REFERENCE
14 VREF
PFC
OUTPUT
DRIVER
12 PFC OUT
RAMP 1 8
RT/CT 7
RAMP 2 9
VDC 6
SS 5
8V VLS
1.25V
VCC
25µA
8V
-
+
÷2
OSCILLATOR
DC LIMIT
VFB
VDC
GREEN
MODE
CONTROLLER
GREEN
MODE
VIN OK
DC ILIMIT
VFB -
+
-
2.43V +
1.5V
-
+
PULSE WIDTH MODULATOR
PWM
OUTPUT
DRIVER
11 PWM OUT
REV. 1.0.1 12/12/2000
1 page  
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
REFERENCE
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Variation
Long Term Stability
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
Output High Voltage
PWM
DC
VOL
Rise/Fall Time
Duty Cycle Range
Output Low Voltage
VOH Output High Voltage
SUPPLY
Rise/Fall Time
Start-up Current
Operating Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
CONDITIONS
TA = 25ºC, I(VREF) = 1mA
11V < VCC < 16.5V
1mA < I(VREF) < 10mA
Line, Load, Temp
TJ = 125ºC, 1000 Hours
VIEAO > 4.0V
VIEAO < 1.2V
IOUT = –20mA
IOUT = –100mA
IOUT = –10mA, VCC = 11V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
IOUT = –20mA
IOUT = –100mA
IOUT = –10mA, VCC = 11V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
VCC = 12V, CL = 0
VCC = 14V, CL = 0
Note 1:
Note 2:
Note 3:
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Includes all bias currents to other circuits connected to the VFB pin.
Gain = K x 5.3V; K = (IMULO - IOFFSET) x IAC x (VEAO - 1.5V)-1.
ML4802
MIN TYP MAX UNITS
7.4 7.5 7.6 V
2 30 mV
2 20 mV
0.4 %
7.35
7.65
V
5 25 mV
0%
85 90
%
0.4 0.8 V
0.7 2.0 V
0.8 1.5 V
VCC - 0.8
V
VCC - 2.0
V
50 ns
0-44
VCC - 0. 8
VCC - 2.0
0-47
0.4
0.7
0.8
50
0-50
0.8
2.0
1.5
%
V
V
V
V
V
ns
200 350 µA
5 7 mA
12 13 14 V
2.5 2.8 3.1 V
REV. 1.0.1 12/12/2000
5
5 Page 
ML4802
FUNCTIONAL DESCRIPTION (Continued)
PWM SECTION
Pulse Width Modulator
The PWM section of the ML4802 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at twice the PFC frequency in the ML4802). The
PWM is primarily intended for current-mode operation. In
current-mode applications, the PWM ramp (RAMP 2) is
usually derived directly from a current sensing resistor in
the primary of the output stage, and is thereby
representative of the current flowing in the converter’s
output stage. DC ILIMIT, which provides cycle-by-cycle
current limiting, is internally connected to RAMP 2.
No voltage error amplifier is included in the PWM stage
of the ML4802, as this function is generally performed on
the output side of the PWM’s isolation boundary. To
facilitate the design of optocoupler feedback circuitry, an
offset has been built into the PWM’s RAMP 2 input which
allows VDC to command a zero percent duty cycle for
input voltages below 1.25V.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the
PFC and inhibits the PWM if this voltage on VFB is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
Solving for the minimum value of CSS:
CSS = 5ms 25mA @ 200nF
1.25V
Caution should be exercised when using this minimum
soft start capacitance value because premature charging of
the SS capacitor and activation of the PWM section can
result if VFB is in the hysteresis band of the VIN OK
comparator at start-up. The magnitude of VFB at start-up is
related both to line voltage and nominal PFC output
voltage. Typically, a 1.0µF soft start capacitor will allow
time for VFB and PFC out to reach their nominal values
prior to activation of the PWM section at line voltages
between 90Vrms and 265Vrms.
Generating VCC
The ML4802 is a voltage-fed part. It requires an external
15V±10% (or better) Zener shunt voltage regulator, or
other controlled supply, to maintain the voltage supplied
to the part at 15V nominal. This allows a low power
dissipation while at the same time delivering 13V
nominal of gate drive at the PWM OUT and PFC OUT
outputs.
LEADING/TRAILING MODULATION
PWM Control (RAMP 2)
RAMP 2 is the sampling point for a voltage representing
the current in the primary of the PWM’s output
transformer, derived from a current sensing resistor.
PWM Current Limit
The DC ILIMIT pin is a cycle-by-cycle current limiter for
the PWM section. It is connected internally to the PWM
control pin. Should the input voltage at this pin ever
exceed 1.5V, the output of the PWM will be disabled until
the output flip-flop is reset by the clock pulse at the start
of the next PWM power cycle.
Soft Start
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON of
the switch. Figure 5 shows a typical trailing edge control
scheme.
L1
I1
+
VIN
DC
SW2 I2
I3
I4
SW1
RL
C1 RAMP
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 25µA
supplies the charging current for the capacitor, and start-
up of the PWM begins at 1.25V. Start-up delay can be
programmed by the following equation:
CSS = tDELAY 25mA
1.25V
where CSS is the required soft start capacitance, and
tDELAY is the desired start-up delay.
REV. 1.0.1 12/12/2000
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
VEAO
VSW1
TIME
TIME
Figure 5. Typical Trailing Edge Control Scheme
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ML4802IS.PDF ] | |
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