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PDF ML4425CP Data sheet ( Hoja de datos )
| Número de pieza | ML4425CP | |
| Descripción | Sensorless BLDC Motor Controller | |
| Fabricantes | Micro Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML4425CP (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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July 2000
ML4425
Sensorless BLDC Motor Controller
GENERAL DESCRIPTION
The ML4425 PWM motor controller provides all of the
functions necessary for starting and controlling the speed
of delta or wye wound Brushless DC (BLDC) motors
without Hall Effect sensors. Back EMF voltage is sensed
from the motor windings to determine the proper
commutation phase sequence using a PLL. This patented
sensing technique will commutate a wide range of 3-
Phase BLDC motors and is insensitive to PWM noise and
motor snubbing circuitry.
The ML4425 limits the motor current using a constant off-
time PWM control loop. The velocity loop is controlled
with an onboard amplifier. The ML4425 has circuitry to
ensure that there is no shoot-through in directly driven
external power MOSFETs.
The timing of the start-up sequence is determined by the
selection of three timing capacitors. This allows
optimization for a wide range of motors and loads.
FEATURES
s Stand-alone operation
s Motor starts and stops with power to IC
s On-board start sequence: Align ® Ramp ® Set Speed
s Patented Back-EMF commutation technique provides
jitterless torque for minimum “spin-up” time
s Onboard speed control loop
s PLL used for commutation provides noise immunity
from PWM spikes, compared to noise sensitive zero
crossing technique
s PWM control for maximum efficiency
s Direct FET drive for 12V motors; drives high voltage
motors with IC buffers from IR, IXYS, Harris, Power
Integrations, Siliconix, etc.
BLOCK DIAGRAM (Pin Configuration Shown for 28 Pin Version)
FB A
22
FB B
23
FB C
24
17
VDD CAT
750nA
1.5V
–
+
BACK
EMF
SAMPLER
19
VDD
CRT
750nA
–
1.5V
+
21
CRR
20 15
SPEED CVCO
FB
16
RVCO
VDD
500nA
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
13
VCO
OUT
8
SPEED SET
+
–
3.9V
5
SPEED COMP
CT
6
1.7V
ISENSE
1
ILIMIT
12
20kHz
1.7V
VCO
OUT
–
+
×5
VREF
16kΩ
–
+
R
A
FB
EC
D
ILIMIT
1-SHOT
8kΩ
CIOS
26
COMMUTATION
STATE MACHINE
1.4V
VDD
–
+
4kΩ
UVLO
GATING
LOGIC
&
OUTPUT
DRIVERS
HA
2
HB
3
HC
4
LA
9
LB
10
LC
11
UV FAULT
18
REFERENCE
BRAKE
25
VDD
GND
RREF
VREF
14
28 27
7
1
1 page  
ELECTRICAL CHARACTERISTICS (Continued)
ML4425
SYMBOL
PARAMETER
LOGIC INPUTS (BRAKE) (Note 3)
CONDITIONS
MIN
TYP
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Current
IIL Input Low Current
LOGIC OUTPUTS (VCO/TACH, UV FAULT) (Note 3)
VIH = 2.4V
VIL = 0.4V
2
2.4
2.9
VCO/TACH Output High Voltage
VCO/TACH Output Low Voltage
UV FAULT Output High Voltage
IOUT = –100µA
IOUT = 400µA
IOUT = –10µA
2.2
C Suffix
I Suffix
3.4
3.2
4.5
UV FAULT Output Low Voltage
BACK-EMF SAMPLER
IOUT = 400µA
SPEED FB Align Mode Voltage
125
SPEED FB Ramp Mode Current
C Suffix 500
I Suffix 500
SPEED FB Run Mode Current
OUTPUT DRIVERS
State A, CRT = 5V,
C Suffix
VPHB = VDD/3
I Suffix
State A, CRT = 5V, VPHB = VDD/2
State A, CRT = 5V,
C Suffix
VPHB = 2´VDD/3
I Suffix
30
27
–15
–90
–90
High Side Driver Output Low Current
High Side Driver Output High Voltage
Low Side Driver Output Low Voltage
Low Side Driver Output High Voltage
VHX = 2V
IHX = –10µA
ILX = 1mA
V(ISENSE) = 0V
SUPPLY
Phase C Cross-conduction Lockout Threshold
0.5
VCC – 1.3
0.2
C Suffix VDD – 2.2
I Suffix VDD – 2.9
VDD – 3.0
IDD VDD Current
UVLO Threshold
C Suffix 8.8
32
9.5
I Suffix 8.6
UVLO Hysteresis
150
MAX
0.8
0.6
5.4
5.6
0.6
250
720
750
90
90
15
–30
–27
1.2
0.7
50
10.2
10.3
UNITS
V
V
mA
mA
V
V
V
V
V
mV
nA
nA
µA
µA
µA
µA
µA
mA
V
V
V
V
V
mA
V
V
mV
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2: For explanation of states, see Figure 4 and Table 1.
Note 3: The BRAKE and UV FAULT pins each have an internal 4kW resistor to the internal reference.
5
5 Page 
ML4425
CRR TO
SPEED FB
FILTER
CAT CRT
FB A
FB B
FB C
VDD CAT
750nA
1.5V
–
+
BACK
EMF
SAMPLER
VDD
CRT
750nA
–
1.5V
+
TO RESET INPUT
OF COMMUTATION
STATE MACHINE
CRR SPEED CVCO
FB
RVCO
VDD
500nA
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times
Run Mode (Back EMF Sensing)
At the end of ramp mode the controller goes into run
mode. In run mode, the back EMF sensing is enabled and
commutation is now under the control of the phase locked
loop. Motor speed is now regulated by the speed control
loop.
PWM SPEED CONTROL
Speed control is accomplished by setting a speed
command at SPEED SET with an input voltage from 0 to
6.9V (VREF). The accuracy of the speed command is
determined by the external components RVCO and CVCO.
There are a number of methods that can be used to control
the speed command of the ML4425. One is to use a 10kW
potentiometer from VREF to ground with the wiper
connected to SPEED SET. If SPEED SET is controlled from
a microcontroller, one of its DACs can be used with VREF
as its input reference.
The speed command is compared with the sensed speed
from SPEED FB through a transconductance error
amplifier. The output of the speed error amplifier is SPEED
COMP. SPEED COMP is clamped between one diode drop
above 3.9V (approximately 4.6V) and one diode drop
below 1.7V (approximately 1V) to prevent speed loop
“wind-up”. Speed loop compensation components are
connected to this pin as shown in Figure 9. The speed loop
compensation components are calculated as follows:
CSC
=
fSB
26.9 N VMOTOR CVCO
Ke 2.5 + 98.696 tm2 fSB2
RSC
=
2p
10
fSB
CSC
(9a)
(9b)
Where fSB is the speed loop bandwidth in Hz.
VREF
10kΩ
RSC
CSC
CT
FROM
SPEED FB
+
–
SPEED SET
3.9V
SPEED COMP
1.7V
CT
1.7V
20kHz
TO
GATING
LOGIC &
OUTPUT
DRIVERS
–
+
PWM ON/OFF
FROM ILIMIT
ONE-SHOT
Figure 9. Speed Control Loop Component Connections
The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp
oscillator creates a sawtooth function from 1.7V to 3.9V
as shown in Figure 9. A negative clamp at one diode drop
below 1.7V (approximately 1V) starts the oscillator on
power up. The frequency of the ramp oscillator is set by a
capacitor to ground CIOS and is selected using the
following equation:
1 50mA
CT
=
fPWM
2.4V
(10)
Where fPWM is the PWM frequency in Hz. The PWM duty
cycle from the speed control loop is gated the current
limit one shot that controls the LA, LB, and LC output
drivers.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ML4425CP.PDF ] | |
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