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ML2008CQ Schematic ( PDF Datasheet ) - Micro Linear

Teilenummer ML2008CQ
Beschreibung P Compatible Logarithmic Gain/Attenuator
Hersteller Micro Linear
Logo Micro Linear Logo 




Gesamt 11 Seiten
ML2008CQ Datasheet, Funktion
March 1997
ML2008*, ML2009**
µP Compatible Logarithmic Gain/Attenuator
GENERAL DESCRIPTION
The ML2008 and ML2009 are digitally controlled
logarithmic gain/attenuators with a range of –24 to +24dB
in 0.1dB steps.
Easy interface to microprocessors is provided by an input
latch and control signals consisting of chip select and
write.
The interface for gain setting of the ML2008 is by an 8-bit
data word, while the ML2009 is designed to interface to a
16-bit data bus with a single write operation by hard-
wiring the gain/attenuation pin or LSB pin. The ML2008
can be power downed by the microprocessor utilizing a
bit in the second write operation.
Absolute gain accuracy is 0.05dB max over supply
tolerance of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for
a wide variety of applications in telecom, audio, sonar or
general purpose function generation.
FEATURES
s Low noise
0dBrnc max with +24dB gain
s Low harmonic distortion
–60dB max
s Gain range
–24 to +24dB
s Resolution
0.1dB steps
s Flat frequency response
±0.05dB from 0.3-4kHz
±0.10dB from 0.1-20kHz
s Low supply current
4mA max from ±5V supplies
s TTL/CMOS compatible digital interface
s ML2008 is designed to interface to an 8-bit data bus;
ML2009 to 16-bit data bus
* This Part Is End Of Life As Of August 1, 2000
** This Part Is Obsolete
BLOCK DIAGRAM
ML2008
ML2009*
VCC VSS GND AGND
VCC VSS GND AGND
+5
VIN
WR
CS
A0
–5
+
COARSE
RESISTORS/
SWITCHES
16
+
FINE
RESISTORS/
SWITCHES
16
+
BUFFER
VOUT
DECODERS
8
REGISTER 0
1
PDN
1
REGISTER 1
8
D1–D8
+5
VIN
WR
CS
–5
+
COARSE
+
FINE
RESISTORS/
SWITCHES
16
RESISTORS/
SWITCHES
16
DECODERS
9
REGISTER 0
9
D0–D8
+
BUFFER
VOUT
1






ML2008CQ Datasheet, Funktion
ML2008, ML2009
TYPICAL PERFORMANCE CURVES (Continued)
100
ATTEN: VIN = 8dBm
90 GAIN: VIN = 8dBm/GAIN SETTING
1kHZ
80
70
60
50
40
–24
–18 –12
–6
0
6
GAIN SETTING (dB)
12 18
Figure 6. CMSG S/N vs Gain Setting
24
0.1
.08
.06
.04
.02
0
–.02
–.04
–.06
–.08
–1.0
–24
–18 –12 –6
0
6 12 18
GAIN SETTING (dB)
Figure 7. Gain Error vs Gain Setting
24
80
VIN = 1kHz
70
60 VIN = 20kHz
50
40
30
20 ATTEN: VIN = 2VRMS
GAIN: VIN = 2VRMS/GAIN SETTING
10
VIN = 50kHz
–24 –18 –12 –6 0 6 12
GAIN SETTING (dB)
18
24
Figure 8. S/N +D vs Gain Setting (VIN/VOUT = 2VRMS)
80
70 VIN = 1kHz
VIN = 20kHz
60
VIN = 50kHz
50
40
30
ATTEN: VIN = 0.5VRMS
GAIN: VIN = 0.5VRMS/GAIN SETTING
20
–24 –18 –12 –6
0
6
GAIN SETTING (dB)
12 18 24
Figure 9. S/N +D vs Gain Setting (VIN/VOUT = 0.5VRMS)
1.0 FUNCTIONAL DESCRIPTION
The ML2008, ML2009 consists of a coarse gain stage, a
fine gain stage, an output buffer, and a µP compatible
parallel digital interface.
1.1 Gain Stages
The analog input, VIN, goes directly into the op amp input
in the coarse gain stage. The coarse gain stage has a gain
range of 0 to 22.5dB in 1.5dB steps.
The fine gain stage is cascaded onto the coarse section.
The fine gain stage has a gain range of 0 to 1.5dB in 0.1dB
steps.
Both stages can be programmed for either gain or
attenuation, thus doubling the effective gain range.
The logarithmic steps in each gains stage are generated by
placing the input signal across a resistor string of 16 series
resistors. Analog switches allow the voltage to be tapped
from the resistor string at 16 points. The resistors are sized
such that each output voltage is at the proper logarithmic
ratio relative to the input signal at the top of the string.
Attenuation is implemented by using the resistor string as
a simple voltage divider, and gain is implemented by
using the resistor string as a feedback resistor around an
internal op amp.
1.2 Gain Settings
Since the coarse and fine gain stages are cascaded, their
gains can be summed logarithmically. Thus, any gain from
–24dB to +24dB in 0.1dB steps can be obtained by
combining the coarse and fine gain setting to yield the
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