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PDF MK1573-02S Data sheet ( Hoja de datos )
| Número de pieza | MK1573-02S | |
| Descripción | GenClock HSYNC to Video Clock | |
| Fabricantes | Integrated Circuit Systems | |
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MK1573-02
GenClock™ HSYNC to Video Clock
Description
The MK1573 GenClock™ provides genlock
timing for video overlay systems. The device
accepts the horizontal sync (HSYNC) signal as the
input reference clock, and generates a frequency-
locked high speed output. Stored in the device are
the multipliers for 16 combinations of popular
frequencies for analog and digital TV and set-top
box systems. Frequency-locked outputs include
1X, 4X, and 8X the subcarrier frequencies of
NTSC and PAL systems, and 27MHz plus
13.5MHz for digital video systems. In most
selections, the chip recovers the HSYNC clock by
outputting a low jitter 50% duty cycle version of
HSYNC. Also available is an inverted recovered
HSYNC clock, and a double speed recovered
HSYNC clock.
MicroClock can customize this device for any
other different frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• The -02 version has one frequency changed
(32MHz was added), and tracks the HSYNC
better than the -01 version.
• Exact ratios stored in the device eliminate the need
for external dividers
• Accepts HSYNC of 15.625kHz or 15.73426kHz
• Highly accurate frequency generation within 1 ppm
• Generates NTSC/PAL subcarrier frequencies, and
4X and 8X of those frequencies
• Generates 27MHz and 13.5MHz
• 2X HSYNC clock available
• Recovered HSYNC clock available
• Inverted HSYNC clock available
• 4.5V to 5.5V operation
Block Diagram
FS0-3 4
HSYNC
Input Clock
VDD GND
22
Input
Buffer
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
CLK3
OE (all outputs)
MDS 1573-02 B
1
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
1 page  
MK1573-02
GenClock™ HSYNC to Video Clock
Clock Waveforms
In addition to generating the video clock on CLK1 (pin 10), the MK1573 also outputs the recovered
HSYNC clocks. On certain selections, a double speed recovered HSYNC clock is also available. These
recovered clocks will have lower jitter than the HSYNC input due to the filtering action of the PLL. The
jitter spectrum of the recovered clocks will be reduced at frequencies higher than the loop bandwidth. The
above section describes how to calculate the approximate loop bandwidth. The waveforms of the
recovered clocks fall into one of three different groups depending on the address selection:
Addresses 0 to 7 and C
HSYNC
input
CLK3
Addresses A and B
HSYNC
input
CLK2
CLK3
Addresses D, E, and F
HSYNC
input
CLK2
CLK3
The recovered clocks are triggered by the falling edge of HSYNC and are delayed by about 100ns.
MDS 1573-02 B
5
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MK1573-02S.PDF ] | |
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