PDF MK1491-06RLFTR Data sheet ( Hoja de datos )

Número de pieza	MK1491-06RLFTR
Descripción	AMD Geode Clock Source
Fabricantes	Integrated Circuit Systems
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No Preview Available ! MK1491-06 AMD Geode™ Clock Source Description The MK1491-06 is a low-cost, low-jitter, high-performance clock synthesizer for AMD’s Geode-based computer and portable appliance applications. Using patented analog Phased-Locked Loop (PLL) techniques, the device accepts a 14.318 MHz crystal input to produce multiple output clocks. It provides selectable PCI local bus and AC97 audio clocks, 24 MHz and 48 MHz clocks for Super I/O and USB, as well as multiple Reference outputs. The device has multiple power-down modes to reduce power consumption. Block Diagram Features • Packaged in 28-pin SOIC or in 28-pin SSOP • Available in Pb (lead) free • Provides all critical timing for the AMD Geode companion chip • Four PCI clocks • Selectable PCIF on up to 2 outputs • Early PCI clock selectability • Up to 4 Reference clocks • 48 MHz USB and 24MHz SIO support • AC97 audio clock • Multiple power down modes • Low EMI Enable pin reduces EMI radiation on PCI clocks (patented) • Operating voltage of 3.3 V ±5% VDD 6 GND 5 PCI Frequency Select Low EMI Enable PCIF Function Enable Early PCI Enable SLOW# PCISTP# PWRDWN# 2 PCI Clocks 3 PCI EPCI/PCI Audio Select 14.3M/24M Select 14.31818 MHz crystal XI XO Crystal Oscillator Audio Clock Fixed Clocks MUX 16.394 MHz or 24.576 MHz or 49.152 MHz 48 MHz 14.318 MHz or 24 MHz 3 14.318 MHz MDS 1491-06 J 1 Revision 110204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 1 page MK1491-06 AMD Geode™ Clock Source External Components The MK1491-06 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be connected on each VDD pin to ground, as close to the MK1491-06 as possible. A series termination resistor of 33Ω may be used for each clock output. See the discussion below for other external resistors required for proper I/O operation. The 14.3 MHz oscillator has internal caps that provide the proper load for a parallel resonant crystal with CL=18 pF. For tuning with other values of CL, the formula 2(CL-18) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground. I/O Structure The MK1491-06 provides more functionality in a 28-pin package by using a unique I/O technique. The device checks the status of all I/O pins during power-up and at exit from the Power Down state. This status (pulled high, low, or mid-level) then determines the frequency selections and power down modes (see the tables on pages 2 and 4). Within 10ms after power up, the inputs change to outputs and the clocks start up. In the diagrams to the right, the 33Ω resistors are the normal output termination resistors. The 10kΩ resistor pulls low to generate a logic zero. Weak internal pull-up resistors are present on SEL24, EPCI#, FS, LE#, PCISTP#, and SLOW#. These pins should be connected directly to VDD or GND if not under active control. Internal resistors on PEN, SEL AUDIO, and TS pull to a mid-level (M). For select = 0 (low) I/O 10 k 33 To load Do not stuff for “1” selection *Note: Do not use a TTL load. This will overcome the 10 kΩ pull-down and force the input to a logic 1. MDS 1491-06 J 5 Revision 110204 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 5 Page

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