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PDF MAX1200 Data sheet ( Hoja de datos )
| Número de pieza | MAX1200 | |
| Descripción | +5v sINGLE-sUPPLY / 1mSPS / 16-bIT sELF-cALIBRATING adc | |
| Fabricantes | Maxim Integrated | |
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19-1413; Rev 0; 12/98
EVAALVUAAILTAIOBNLEKIT
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
General Description
The MAX1200 16-bit, monolithic, analog-to-digital con-
verter (ADC) is capable of conversion rates up to
1Msps. This CMOS integrated circuit uses a fully differ-
ential, pipelined architecture with digital error correction
and a short self-calibration to ensure 16-bit linearity at
full sample rates. An on-chip track/hold (T/H) maintains
superb dynamic performance up to the Nyquist frequen-
cy. The MAX1200 operates from a single +5V supply.
The fully differential inputs allow an input swing of
±VREF. The reference is also differential with the posi-
tive reference (RFPF) typically connected to +4.096V
and the negative reference (RFNF) connected to ana-
log ground. Additional sensing pins (RFPS, RFNS) are
provided to compensate for any resistive divider action
that may occur. A single-ended input is also possible
using two operational amplifiers.
Power dissipation is typically only 273mW at +5V, at a
sampling rate of 1Msps. The device employs a CMOS-
compatible, 16-bit parallel, two’s complement output
data format. For a higher sampling speed (up to
2.2Msps) but lower resolution (14-bit), select the
MAX1201, a pin-compatible version of the MAX1200.
The MAX1200 is available in an MQFP package and
operates over the commercial (0°C to +70°C) and
extended-industrial (-40°C to +85°C) temperature
ranges.
High-Resolution Imaging
Communications
Scanners
Data Acquisition
Instrumentation
Applications
Features
o Monolithic 16-Bit, 1Msps A/D Converter
o Single +5V Supply
o ±VREF Differential Input Voltage Range
o 87dB SNR for fIN = 100kHz
o 91dB SFDR for fIN = 100kHz
o 273mW Low-Power Dissipation
o ±0.5LSB Differential Nonlinearity Error
o Three-State, Two’s Complement Output Data
o On-Demand Self-Calibration
o Pin-Compatible 14-Bit Versions Available
(1Msps MAX1205, 2.2Msps MAX1201)
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
DNL
(LSB)
MAX1200ACMH
MAX1200BCMH
MAX1200AEMH
MAX1200BEMH
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
44 MQFP
44 MQFP
44 MQFP
44 MQFP
±0.5
—
±0.5
—
Pin Configuration
TOP VIEW
ST_CAL
AGND
AVDD
AGND
AGND
AVDD
DOR
D15
D14
D13
D12
1
2
3
4
5
6
7
8
9
10
11
MAX1200
33 OE
32 DAV
31 CLK
30 DVDD
29 DGND
28 DGND
27 DVDD
26 TEST1
25 D0
24 D1
23 D2
MQFP
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
__________________________________________Typical Operating Characteristics
(AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND; VCM = +2.048V, differential input, fCLK = 2.048MHz,
calibrated, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
5
4
3
2
1
0
-1
-2
-3
-4
-5
-32768
-16384
0
16384 32768
TWO’S COMPLEMENT OUTPUT CODE
DIFFERENTIAL NONLINEARITY vs.
TWO’S COMPLEMENT OUTPUT CODE
1.0
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.0
-32,768 -16,384 0 16,384 32,768
TWO’S COMPLEMENT OUTPUT CODE
SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT AMPLITUDE (fIN = 99.5kHz)
120
(dBFS)
110
100
90
80
70
(dBc)
60
50
40
30
-80 -70 -60 -50 -40 -30 -20 -10
INPUT AMPLITUDE (dBFS)
0
SIGNAL-TO-NOISE RATIO PLUS
DISTORTION vs. INPUT FREQUENCY
86
AIN = -0.5dBFS
84
82
80
78
AIN = -6dBFS
76
74
72
70 AIN = -20dBFS
68
1
10 100
INPUT FREQUENCY (kHz)
1000
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
-74
-76
AIN = -20dBFS
-78
-80
-82 AIN = -6dBFS
-84
-86
-88 AIN = -0.5dBFS
-90
1
10 100
INPUT FREQUENCY (kHz)
1000
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
90
AIN = -0.5dBFS
85
AIN = -6dBFS
80
75
70
65
1
AIN = -20dBFS
10 100
INPUT FREQUENCY (kHz)
1000
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. SAMPLING RATE (fIN = 99.5kHz)
85
84
83
82
81
80
0.1
1
SAMPLE RATE (Msps)
10
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
0
TYPICAL FFT, fIN = 99.5kHz,
8192 VALUE RECORD
200 400
FREQUENCY (kHz)
600
0
-15
-30
-45
-60
-75
-90
-105
-120
-135
-150
0
TYPICAL FFT, fIN = 504.5MHz,
8192 VALUE RECORD
200 400
FREQUENCY (kHz)
600
_______________________________________________________________________________________ 5
5 Page 
+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
Calibration Procedure
Since the MAX1200 is based on a pipelined architec-
ture, low-resolution quantizers (“coarse ADCs”) are
used to approximate the input signal. MDACs of the
same resolution are then used to reconstruct the input
signal, which is subtracted from the input and the
residue amplified by the SC gain stage. This residue is
then passed on to the next stage.
The accuracy of the MAX1200 is limited by the preci-
sion of the MDAC, which is strongly dependent on the
matching of the capacitors used. The mismatch
between the capacitors is determined and stored in an
on-chip memory, which is later used during the conver-
sion of the input signal.
During the calibration procedure, the clock must be
running continuously. ST_CAL (start of calibration) is
initiated by a positive pulse with a minimum width of
four clock cycles, but not longer than about 17,400
clock cycles (Figure 8).
The ST_CAL input may be asynchronous with the clock,
since it is retimed internally. With ST_CAL activated,
END_CAL goes low one or two clock cycles later and
remains low until the calibration is complete. During this
period, the reference voltages must be stable to less
than 0.01%; otherwise the calibration will be invalid.
During calibration, the analog inputs INP and INN are
not used; however, better performance is achieved if
these inputs are static. Once END_CAL goes high (indi-
cating that the calibration procedure is complete), the
ADC is ready for conversion.
Once calibrated, the MAX1200 is insensitive to small
changes (±5%) in power-supply voltage or tempera-
ture. Following calibration, if the temperature changes
more than ±20°C, the device should be recalibrated to
maintain optimum performance.
N
AIN
N+1
tCH
CLK
N+2 N+3
tCL
N+4
N+5
SAMPLE
CLOCK
tS
DAV
D0–D15
tOD
N-3 N-2 N-1
N N+1
CLK
ST_CAL
END_CAL
MIN 4 tCLK
~17,400 CLK CYCLES
Figure 8. Timing for Start and End of Calibration
OE
D0–D15
DOR
tAC
Z
tREL
Z
Z = HIGH IMPEDANCE (THREE-STATED)
Figure 9. Timing for Bus Access and Bus Relinquish—
Controlled by Output Enable (OE)
Two’s Complement Output
The MAX1200 outputs data in two’s complement for-
mat. Table 1 shows how to convert the various full-
scale inputs into their two’s complement output codes.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
SNR(MAX) = (6.02 · N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise which
includes all spectral components minus the fundamen-
tal, the first nine harmonics, and the DC offset.
Figure 7. Main Timing Diagram
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX1200.PDF ] | |
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