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M95010 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M95010
Beschreibung 4Kbit / 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
M95010 Datasheet, Funktion
M95040
M95020, M95010
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM
With High Speed Clock
FEATURES SUMMARY
s Compatible with SPI Bus Serial Interface
(Positive Clock SPI Modes)
s Single Supply Voltage:
– 4.5V to 5.5V for M950x0
– 2.5V to 5.5V for M950x0-W
– 1.8V to 3.6V for M950x0-S
s 5 MHz Clock Rate (maximum)
s Status Register
s BYTE and PAGE WRITE (up to 16 Bytes)
s Self-Timed Programming Cycle
s Adjustable Size Read-Only EEPROM Area
s Enhanced ESD Protection
s More than 1,000,000 Erase/Write Cycles
s More than 40 Year Data Retention
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
July 2003
1/33






M95010 Datasheet, Funktion
M95040, M95020, M95010
OPERATING FEATURES
Power-up
When the power supply is turned on, VCC rises
from VSS to VCC.
During this time, the Chip Select (S) must be al-
lowed to follow the VCC voltage. It must not be al-
lowed to float, but should be connected to VCC via
a suitable pull-up resistor.
As a built in safety feature, Chip Select (S) is edge
sensitive as well as level sensitive. After Power-
up, the device does not become selected until a
falling edge has first been detected on Chip Select
(S). This ensures that Chip Select (S) must have
been High, prior to going Low to start the first op-
eration.
Power-down
At Power-down, the device must be deselected.
Chip Select (S) should be allowed to follow the
voltage applied on VCC.
Active Power and Stand-by Power Modes
When Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode. The device
consumes ICC, as specified in Tables 12 to 16.
When Chip Select (S) is High, the device is dis-
abled. If an Erase/Write cycle is not currently in
progress, the device then goes in to the Stand-by
Figure 6. Hold Condition Activation
Power mode, and the device consumption drops
to ICC1.
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
Normally, the device is kept selected, for the whole
duration of the Hold condition. Deselecting the de-
vice while it is in the Hold condition, has the effect
of resetting the state of the device, and this mech-
anism can be used if it is required to reset any pro-
cesses that had been in progress.
The Hold condition starts when the Hold (HOLD)
signal is driven Low at the same time as Serial
Clock (C) already being Low (as shown in Figure
6).
The Hold condition ends when the Hold (HOLD)
signal is driven High at the same time as Serial
Clock (C) already being Low.
Figure 6 also shows what happens if the rising and
falling edges are not timed to coincide with Serial
Clock (C) being Low.
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
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6 Page









M95010 pdf, datenblatt
M95040, M95020, M95010
Figure 10. Read Status Register (RDSR) Sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q 76543210765432107
MSB
MSB
AI01444D
Read Status Register (RDSR)
One of the major uses of this instruction is to allow
the MCU to poll the state of the Write In Progress
(WIP) bit. This is needed because the device will
not accept further WRITE or WRSR instructions
when the previous Write cycle is not yet finished.
As shown in Figure 10, to send this instruction to
the device, Chip Select (S) is first driven Low. The
bits of the instruction byte are then shifted in, on
Serial Data Input (D). The current state of the bits
in the Status Register is shifted out, on Serial Data
Out (Q). The Read Cycle is terminated by driving
Chip Select (S) High.
The Status Register may be read at any time, even
during a Write cycle (whether it be to the memory
area or to the Status Register). All bits of the Sta-
tus Register remain valid, and can be read using
the RDSR instruction. However, during the current
Write cycle, the values of the non-volatile bits
(BP0, BP1) become frozen at a constant value.
The updated value of these bits becomes avail-
able when a new RDSR instruction is executed, af-
ter completion of the Write cycle. On the other
hand, the two read-only bits (Write Enable Latch
(WEL), Write In Progress (WIP)) are dynamically
updated during the on-going Write cycle.
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle
is in progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write or Write Status Register in-
struction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Write instructions.
These bits are written with the Write Status Regis-
ter (WRSR) instruction. When one or both of the
Block Protect (BP1, BP0) bits is set to 1, the rele-
vant memory area (as defined in Table 3) be-
comes protected against Write (WRITE)
instructions. The Block Protect (BP1, BP0) bits
can be written provided that the Hardware Protect-
ed mode has not been set.
12/33

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