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M88 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M88
Beschreibung In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems with CPLD for MCUs
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 7 Seiten
M88 Datasheet, Funktion
M88 FAMILY
In-System Programmable (ISP) Multiple-Memory and
Logic FLASH+PSD Systems (with CPLD) for MCUs
DATA BRIEFING
s Single Supply Voltage:
– 5 V±10% for M88xxFxY
– 3 V (+20/–10%) for M88xxFxW
s 1 or 2 Mbit of Primary Flash Memory (8 uniform
sectors, 16K x 8, or 32K x 8)
s A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8813F1x)
or Flash memory (for M88x3F2x)
– 4 uniform sectors (8K x 8)
s SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)
s Over 3,000 Gates of PLD: DPLD and CPLD
s 27 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s Stand-by current:
– 50 µA for M88xxFxY
– 25 µA for M88xxFxW
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
DESCRIPTION
The FLASH+PSD family of memory systems for
microcontrollers (MCUs) brings In-System-
Table 1. Signal Names
PA0-PA7
Port-A
PB0-PB7
Port-B
PC0-PC7
Port-C
PC2 = Voltage Stand-by
PD0-PD2
AD0-AD15
Port-D
Address/Data
CNTL0-CNTL2
RESET
Control
Reset
VCC Supply Voltage
VSS Ground
PQFP52 (T)
PLCC52 (K)
Figure 1. Logic Diagram
VCC
8
PA0-PA7
3
CNTL0-
CNTL2
16
AD0-AD15
FLASH+PSD
8
PB0-PB7
8
PC0-PC7
RESET
3
PD0-PD2
VSS
AI02856
June 2000
Complete data available on Data-on-Disc CD-ROM or at www.st.com
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M88 Datasheet, Funktion
M88 FAMILY
Table 6. Ordering Information Scheme
Example:
M88 1 3 F 1 W – 15
T
1T
SRAM Capacity
1 16 Kbit
3 64 Kbit
Flash Memory Capacity
3 1 Mbit (128K x 8)
4 2 Mbit (256K x 8)
2nd Non Volatile Memory
1 256 Kbit EEPROM
2 256 Kbit Flash memory
Operating Voltage
Y 4.5 V to 5.5 V
W 2.7 V to 3.6 V
Note: 1. Available on the 4.5 to 5.5 V range, only.
ORDERING INFORMATION SCHEME
When delivered from ST, the FLASH+PSD device
has all bits in the memory and PLDs set to 1. The
FLASH+PSD Configuration Register bits are set to
0. The code, configuration, and PLD logic are
loaded using the programming procedure.
Information for programming the device is
available directly from ST. Please contact your
local sales representative.
The notation used for the device number is as
shown in Table 6. For a list of available options
(speed, package, etc.) or for further information on
any aspect of this device, please see the full data
sheet (please consult our pages on the world wide
web: www.st.com/flashpsd). Alternatively, please
contact your nearest ST Sales Office.
Option
T Tape & Reel Packing
Temperature Range
1 0 to 70 °C (commercial)
6 –40 to 85 °C (industrial)
Package
K PLCC52
T PQFP52
Speed
-90 90 ns1
-15 150 ns
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