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M82C288-8 Schematic ( PDF Datasheet ) - Intel

Teilenummer M82C288-8
Beschreibung BUS CONTROLLER FOR M80286 PROCESSORS
Hersteller Intel
Logo Intel Logo 




Gesamt 20 Seiten
M82C288-8 Datasheet, Funktion
M82C288
BUS CONTROLLER FOR M80286 PROCESSORS
(M82C288-10 M82C288-8 M82C288-6)
Military
Y Provides Commands and Controls for
Local and System Bus
Y Wide Flexibility in System
Configurations
Y Implemented in High Speed CHMOS III
Technology
Y Fully Compatible with the HMOS
M82288
Y Fully Static Device
Y Single a5V Supply
Y Available in 20 Pin Cerdip Package
(See Packaging Spec Order 231369)
The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The
M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and
supports a low power mode The bus controller provides command and control outputs with flexible timing
options Separate command outputs are used for memory and I O devices The data bus is controlled with
separate data enable and direction control signals
Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high
speed bus cycles
20 Pin Cerdip Package
Figure 1 M82C288 Block Diagram
271077 – 1
271077 – 2
Figure 2 M82C288 Pin
Configuration
November 1991
Order Number 271077-006






M82C288-8 Datasheet, Funktion
M82C288
Bus State Definition
The M82C288 bus controller has three bus states
(see Figure 4) Idle (TI) Status (TS) and Command
(TC) Each bus state is two CLK cycles long Bus
state phases correspond to the internal CPU proces-
sor clock phases
The TI bus state occurs when no bus cycle is cur-
rently active on the M80286 local bus This state
may be repeated indefinitely When control of the
local bus is being passed between masters the bus
remains in the TI state
Bus Cycle Definition
The S1 and S0 inpus signal the start of a bus cycle
When either input becomes LOW a bus cycle is
started The TS bus state is defined to be the two
CLK cycles during which either S1 or S0 are active
(see Figure 5) These inputs are sampled by the
M82C288 at every falling edge of CLK When either
S1 and S0 are sampled LOW the next CLK cycle is
considered the second phase of the internal CPU
clock cycle
The local bus enters the TC bus state after the TS
state The shortest bus cycle may have one TS state
and one TC state Longer bus cycles are formed by
repeating TC state A repeated TC bus state is called
a wait state
The READY input determines whether the current
TC bus state is to be repeated The READY input
has the same timing and effect for all bus cycles
READY is sampled at the end of each TC bus state
to see if it is active If sampled HIGH The TC bus
state is repeated This is called inserting a wait state
The control and command outputs do not change
during wait states
When READY is sampled LOW the current bus cy-
cle is terminated Note that the bus controller may
enter the TS bus state directly from TC if the status
lines are sampled active at the next falling edge of
CLK
271077 –4
Figure 4 M82C288 Bus States
Figure 5 Bus Cycle Definition
271077 – 5
6

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M82C288-8 pdf, datenblatt
M82C288
CMDLY is first sampled on the falling edge of the
CLK ending TS If sampled HIGH the command out-
put is not activated and CMDLY is again sampled
on the next falling edge of CLK Once sampled
LOW the proper command output becomes active
immediately if MB e 0 If MB e 1 the proper com-
mand goes active no earlier than shown in Figures 9
and 10
READY can terminate a bus cycle before CMDLY
allows a command to be issued In this case no
commands are issued an the bus controller will de-
activate DEN and DT R in the same manner as if a
command has been issued
sitions of all signals in all modes Instead all signal
timing relationships are shown via the general cas-
es Special cases are shown when needed The
waveforms provide some functional descriptions of
the M82C288 however most functional descriptions
are provided in Figures 5 through 11
To find the timing specification for a signal transition
in a particular mode first look for a special case in
the waveforms If no special case applies then use
a timing specification for the same or related func-
tion in another mode
Waveforms Discussion
The waveforms show the timing relationships of in-
puts and outputs and do not show all possible tran-
12

12 Page





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