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PDF M80C286 Data sheet ( Hoja de datos )
| Número de pieza | M80C286 | |
| Descripción | HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION | |
| Fabricantes | Intel | |
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M80C286
HIGH PERFORMANCE CHMOS MICROPROCESSOR
WITH MEMORY MANAGEMENT AND PROTECTION
Military
Y High Speed CHMOS III Technology
Y Pin for Pin Clock for Clock and
Functionally Compatible with the HMOS
M80286
(See M80286 Data Sheet Order 271028-003)
Y Stop Clock Capability
Uses Less Power (see ICCS
Specification)
Y 10 MHz Clock Rate
Y 68 Lead Pin Grid Array Package
Y 68 Lead Ceramic Quad Flatpack
Package
(See Packaging Spec Order 231369)
Y Military Temperature Range
b55 C to a125 C (TC)
INTRODUCTION
The M80C286 is an advanced 16 bit CHMOS III microprocessor designed for multi-user and multi-tasking
applications that require low power and high performance The M80C286 is fully compatible with its predeces-
sor the HMOS M80286 and object-code compatible with the M8086 and M80386 family of products In
addition the M80C286 has a power down mode which uses less power making it ideal for mobile applications
The M80C286 has built-in memory protection that maintains a four level protection mechanism for task isola-
tion a hardware task switching facility and memory mangement capabilities that map 230 bytes (one gigabyte)
of virtual address space per task (per user) into 224 bytes (16 megabytes) of physical memory
The M80C286 is upward compatible with M8086 and M8088 software Using M8086 real address mode the
M80C286 is object code compatible with existing M8086 M8088 software In protected virtual address mode
the M80C286 is source code compatible with M8086 M8088 software which may require upgrading to use
virtual addresses supported by the M80C286’s integrated memory management and protection mechanism
Both modes operate at full M80C286 performance and execute a superset of the M8086 and M8088 instruc-
tions
The M80C286 provides special operations to support the efficient implementation and execution of operating
systems For example one instruction can end execution of one task save its state switch to a new task load
its state and start execution of the new task The M80C286 also supports virtual memory systems by providing
a segment-not-present exception and restartable instructions
February 1990
Figure 1 M80C286 Internal Block Diagram
271103 – 1
Order Number 271103-001
1 page  
M80C286
Table 2 Instruction Set (Continued)
CONDITIONAL TRANSFERS
JA JNBE
Jump if above not below nor equal
JAE JNB
Jump if above or equal not below
JB JNAE
Jump if below not above nor equal
JBE JNA
Jump if below or equal not above
JC Jump if carry
JE JZ
Jump if equal zero
JG JNLE
Jump if greater not less nor equal
JGE JNL
Jump if greater or equal not less
JL JNGE
Jump if less not greater nor equal
JLE JNG
Jump if less or equal not greater
JNC Jump if not carry
JNE JNZ
Jump if not equal not zero
JNO
Jump if not overflow
JNP JPO
Jump if not parity parity odd
JNS Jump if not sign
JO Jump if overflow
JP JPE
Jump if parity parity even
JS Jump if sign
UNCONDITIONAL TRANSFERS
CALL
Call procedure
RET Return from procedure
JMP Jump
ITERATION CONTROLS
LOOP
Loop
LOOPE LOOPZ
Loop if equal zero
LOOPNE LOOPNZ Loop if not equal not zero
JCXZ
Jump if register CX e 0
INTERRUPTS
INT Interrupt
INTO
Interrupt if overflow
IRET
Interrupt return
FLAG OPERATIONS
STC Set carry flag
CLC Clear carry flag
CMC
Complement carry flag
STD Set direction flag
CLD Clear direction flag
STI Set interrupt enable flag
CLI Clear interrupt enable flag
EXTERNAL SYNCHRONIZATION
HLT Halt until interrupt or reset
WAIT
Wait for BUSY not active
ESC
Escape to extension processor
LOCK
Lock bus during next instruction
NO OPERATION
NOP
No operation
EXECUTION ENVIRONMENT CONTROL
LMSW
Load machine status word
SMSW
Store machine status word
Process Control Instructions
ENTER
LEAVE
BOUND
Format stack for procedure entry
Restore stack for procedure exit
Detects values outside
prescribed range
High Level Instructions
Program Transfer Instructions
Memory Organization
Memory is organized as sets of variable length seg-
ments Each segment is a linear contiguous se-
quence of up to 64K (216) 8-bit bytes Memory is
addressed using a two component address (a point-
er) that consists of a 16-bit segment selector and a
16-bit offset see Figure 4 The segment selector in-
dicates the desired segment in memory The offset
component indicates the desired byte address within
the segment
271103 – 3
Figure 4 Two Component Address
5
5 Page 
M80C286
Table 9 Real Address Mode Addressing Interrupts
Function
Interrupt
Number
Related
Instructions
Return Address
Before Instruction
Interrupt table limit too small exception 8 INT vector is not within table limit
Yes
Processor extension segment overrun
interrupt
9 ESC with memory operand extend-
ing beyond offset FFFF(H)
No
Segment overrun exception
13 Word memory reference with offset
e FFFF(H) or an attempt to exe-
cute past the end of a segment
Yes
Interrupts
Table 9 shows the interrupt vectors reserved for ex-
ceptions and interrupts which indicate an addressing
error The exceptions leave the CPU in the state ex-
isting before attempting to execute the failing in-
struction (except for PUSH POP PUSHA or POPA)
Refer to the next section on protected mode initiali-
zation for a discussion on exception 8
Protected Mode Initialization
To prepare the M80C286 for protected mode the
LIDT instruction is used to load the 24-bit interrupt
table base and 16-bit limit for the protected mode
interrupt table This instruction can also set a base
and limit for the interrupt vector table in real address
mode After reset the interrupt table base is initial-
ized to 000000(H) and its size set to 03FF(H) These
values are compatible with M8086 88 software
LIDT should only be executed in preparation for pro-
tected mode
Shutdown
Shutdown occurs when a severe error is detected
that prevents further instruction processing by the
CPU Shutdown and halt are externally signalled via
a halt bus operation They can be distinguished by
A1 HIGH for halt and A1 LOW for shutdown In real
address mode shutdown can occur under two con-
ditions
Exceptions 8 or 13 happen and the IDT limit does
not include the interrupt vector
A CALL INT or PUSH instruction attempts to wrap
around the stack segment when SP is not even
An NMI input can bring the CPU out of shutdown if
the IDT limit is at least 000F(H) and SP is greater
than 0005(H) otherwise shutdown can only be exit-
ed via the RESET input
PROTECTED VIRTUAL ADDRESS
MODE
The M80C286 executes a fully upward-compatible
superset of the M8086 instruction set in protected
virtual address mode (protected mode) Protected
mode also provides memory management and pro-
tection mechanisms and associated instructions
The M80C286 enters protected virtual address
mode from real address mode by setting the PE
(Protection Enable) bit of the machine status word
with the Load Machine Status Word (LMSW) instruc-
tion Protected mode offers extended physical and
virtual memory address space memory protection
mechanisms and new operations to support operat-
ing systems and virtual memory
All registers instructions and addressing modes de-
scribed in the M80C286 Base Architecture section
of this Functional Description remain the same Pro-
grams for the M8086 88 186 and real address
mode M80C286 can be run in protected mode how-
ever embedded constants for segment selectors
are different
Memory Size
The protected mode M80C286 provides a 1 gigabyte
virtual address space per task mapped into a 16
megabyte physical address space defined by the ad-
dress pin A23–A0 and BHE The virtual address
space may be larger than the physical address
space since any use of an address that does not
map to a physical memory location will cause a re-
startable exception
Memory Addressing
As in real address mode protected mode uses 32-
bit pointers consisting of 16-bit selector and offset
components The selector however specifies an in-
dex into a memory resident table rather than the up-
per 16-bits of a real memory address The 24-bit
base address of the desired segment is obtained
11
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