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M80C186XL12 Schematic ( PDF Datasheet ) - Intel

Teilenummer M80C186XL12
Beschreibung 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
Hersteller Intel
Logo Intel Logo 




Gesamt 44 Seiten
M80C186XL12 Datasheet, Funktion
M80C186XL20 16 12 10
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
Y Low Power Full Static Version of
M80C186
Y Operation Modes
Enhanced Mode
DRAM Refresh Control Unit
Power-Save Mode
Direct Interface to 80C187
Compatible Mode
NMOS 80186 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y Integrated Feature Set
Static Modular CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power-Save Mode
System-Level Testing Support (High
Impedance Test Mode)
Y Completely Object Code Compatible
with Existing 8086 8088 Software and
Has 10 Additional Instructions over
8086 8088
Y Speed Versions Available
20 MHz (M80C186XL20)
16 MHz (M80C186XL16)
12 5 MHz (M80C186XL12)
10 MHz (M80C186XL)
Y Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I O
Y Complete System Development
Support
All 8086 and 80C186 Software
Development Tools Can Be Used for
M80C186XL System Development
ASM 86 Assembler PL M-86
Pascal-86 Fortran-86 iC-86 and
System Utilities
In-Circuit-Emulator (ICETM-186)
Y Available in 68-Pin
Ceramic Pin Grid Array (PGA)
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80C186XL is a Modular Core re-implementation of the M80C186 microprocessor It offers higher
speed and lower power consumption than the standard M80C186 but maintains 100% clock-for-clock func-
tional compatibility Packaging and pinout are also identical
271276 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1995
Order Number 271276-002






M80C186XL12 Datasheet, Funktion
M80C186XL
Symbol
TMR IN 0
TMR IN 1
TMR OUT 0
TMR OUT 1
DRQ0
DRQ1
NMI
INT0
INT1 SELECT
INT2 INTA0
INT3 INTA1 IRQ
A19 S6
A18 S5
A17 S4
A16 S3
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Table 1 M80C186XL Pin Description (Continued)
PGA
Pin No
Type
Name and Function
20 I Timer Inputs are used either as clock or control signals
21 I depending upon the programmed timer mode These inputs are
active HIGH (or LOW-to-HIGH transitions are counted) and
internally synchronized Timer Inputs must be tied HIGH when
not being used as clock or retrigger inputs
22 O Timer outputs are used to provide single pulse or continous
23 O waveform generation depending upon the timer mode selected
These outputs are not floated during a bus hold
18 I DMA Request is asserted HIGH by an external device when it is
19 I ready for DMA Channel 0 or 1 to perform a transfer These
signals are level-triggered and internally synchronized
46 I The Non-Maskable Interrupt input causes a Type 2 interrupt An
NMI transition from LOW to HIGH is latched and synchronized
internally and initiates the interrupt at the next instruction
boundary NMI must be asserted for at least one CLKOUT period
The Non-Maskable Interrupt cannot be avoided by programming
45 I Maskable Interrupt Requests can be requested by activating one
44 I of these pins When configured as inputs these pins are active
42 I O HIGH Interrupt Requests are synchronized internally INT2 and
41 I O INT3 may be configured to provide active-LOW interrupt-
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To ensure
recognition all interrupt requests must remain active until the
interrupt is acknowledged When Slave Mode is selected the
function of these pins changes (see Interrupt Controller section
of this data sheet)
65 O Address Bus Outputs (16 – 19) and Bus Cycle Status (3 – 6)
66 O indicate the four most significant address bits during T1 These
67 O signals are active HIGH
68 O During T2 T3 TW and T4 the S6 pin is LOW to indicate a CPU-
initiated bus cycle or HIGH to indicate a DMA-initiated or refresh
bus cycle During the same T-states S3 S4 and S5 are always
LOW These outputs are floated during bus hold or reset
1 I O Address Data Bus (0 – 15) signals constitute the time multiplexed
3 I O memory or I O address (T1) and data (T2 T3 TW and T4) bus
5 I O The bus is active HIGH A0 is analogous to BHE for the lower
7 I O byte of the data bus pins D7 through D0 It is LOW during T1
10
12
IO
IO
when a byte is to be transferred onto the lower portion of the bus
in memory or I O operations These pins are floated during a bus
hold or reset
14 I O
16 I O
2 IO
4 IO
6 IO
8 IO
11 I O
13 I O
15 I O
17 I O
6

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M80C186XL12 pdf, datenblatt
M80C186XL
The M80C186XL provides a chip select for low
memory called LCS The bottom of memory con-
tains the interrupt vector table starting at location
00000H
The M80C186XL provides four MCS lines which are
active within a user-locatable memory block This
block can be located within the M80C186XL 1 Mbyte
memory address space exclusive of the areas de-
fined by UCS and LCS Both the base address and
size of this memory block are programmable
The M80C186XL can generate chip selects for up to
seven peripheral devices These chip selects are ac-
tive for seven contiguous blocks of 128 bytes above
a programmable base address The base address
may be located in either memory or I O space
The M80C186XL can generate a READY signal in-
ternally for each of the memory or peripheral CS
lines The number of WAIT states to be inserted for
each peripheral or memory is programmable to pro-
vide 0–3 wait states for all accesses to the area for
which the chip select is active In addition the
M80C186XL may be programmed to either ignore
external READY for each chip-select range individu-
ally or to factor external READY with the integrated
ready generator
Upon RESET the Chip-Select Ready Logic will per-
form the following actions
 All chip-select outputs will be driven HIGH
 Upon leaving RESET the UCS line will be pro-
grammed to provide chip selects to a 1K block
with the accompanying READY control bits set at
011 to insert 3 wait states in conjunction with ex-
ternal READY (i e UMCS resets to FFFBH)
 No other chip select or READY control registers
have any predefined values after RESET They
will not become active until the CPU accesses
their control registers
DMA Unit
The M80C186XL DMA controller provides two inde-
pendent high-speed DMA channels Data transfers
can occur between memory and I O spaces (e g
Memory to I O) or within the same space (e g
Memory to Memory or I O to I O) Data can be
transferred either in bytes (8 bits) or in words (16
bits) to or from even or odd addresses Each DMA
channel maintains both a 20-bit source and destina-
tion pointer which can be optionally incremented or
decremented after each data transfer (by one or two
depending on byte or word transfers) Each data
transfer consumes 2 bus cycles (a minimum of 8
clocks) one cycle to fetch data and the other to
store data
Timer Counter Unit
The M80C186XL provides three internal 16-bit pro-
grammable timers Two of these are highly flexible
and are connected to four external pins (2 per timer)
They can be used to count external events time ex-
ternal events generate nonrepetitive waveforms
etc The third timer is not connected to any external
pins and is useful for real-time coding and time de-
lay applications In addition the third timer can be
used as a prescaler to the other two or as a DMA
request source
Interrupt Control Unit
The M80C186XL can receive interrupts from a num-
ber of sources both internal and external The
M80C186XL has 5 external and 2 internal interrupt
sources (Timer Couners and DMA) The internal in-
terrupt controller serves to merge these requests on
a priority basis for individual service by the CPU
Enhanced Mode Operation
In Compatible Mode the M80C186XL operates with
all the features of the NMOS 80186 with the excep-
tion of 8087 support (i e no math coprocessing is
possible in Compatible Mode) Queue-Status infor-
mation is still available for design purposes other
than 8087 support
All the Enhanced Mode features are completely
masked when in Compatible Mode A write to any of
the Enhanced Mode registers will have no effect
while a read will not return any valid data
In Enhanced Mode the M80C186XL will operate
with Power-Save DRAM refresh and numerics co-
processor support in addition to all the Compatible
Mode features
If connected to a math coprocessor this mode will
be invoked automatically Without an NPX this
mode can be entered by tying the RESET output
signal from the M80C186XL to the TEST BUSY in-
put
Queue-Status Mode
The queue-status mode is entered by strapping the
RD pin low RD is sampled at RESET and if LOW
the M80C186XL will reconfigure the ALE and WR
pins to be QS0 and QS1 respectively This mode is
available on the M80C186XL in both Compatible
and Enhanced Modes
12

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SeitenGesamt 44 Seiten
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