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M74HCT374 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M74HCT374
Beschreibung OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HCT374 NON INVERTING - HCT534 INVERTING
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 13 Seiten
M74HCT374 Datasheet, Funktion
M54/74HCT374
M54/74HCT534
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
HCT374 NON INVERTING - HCT534 INVERTING
. HIGH SPEED
fMAX = 62 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS374/534
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCTXXXF1R M74HCTXXXM1R
M74HCTXXXB1R M74HCTXXXC1R
The M54/74HCT374, M54/74HCT534, are high
speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-
STATE OUTPUTS fabricated with in silicon gate
C2MOS technology. They have the same high
speed performance of LSTTL combined with true
CMOS low power comsuption. These8-bit D-type
flip-flops are controlled by a clock input (CK) and an
ouput enable input (OE). On the positive transition
of the clock, the Q outputs will be set to the logic
state that were setup at the D inputs (HCT374) or
their complements (HCT534).
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
while high level, the outputs will be in a high imped-
ance state. The output control does not affect the in-
ternal operation of flip-flops. That is, the old data can
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting and non-in-
verting outputs. The 3-state output configuration
and the wide choice of outline make bus-organized
systems simple. All inputs are equipped with protec-
tion circuits against static discharge and transient
excess voltage. This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC2MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption.
PIN CONNECTION (top view)
April 1993
1/13






M74HCT374 Datasheet, Funktion
M54/M74HCT374/534
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC CL
(V) (pF)
tTLH Output Transition 4.5 50
tTHL Time
tPLH Propagation
4.5 50
tPHL Delay Time
4.5 150
(CLOCK - Q, Q)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
7 12
Value
-40 to 85 oC
74HC
Min. Max.
15
-55 to 125 oC
54HC
Min. Max.
18
Unit
ns
20 30 38 45 ns
25 38 48 57 ns
tPZL Output Enable
4.5 50 RL = 1 K
17 30
38
45 ns
tPZH Time
4.5 150 RL = 1 K
25 38
48
57 ns
tPZL Output Disable
tPZH Time
4.5 50 RL = 1 K
16 28
35
42 ns
fMAX Maximum CLock 4.5 50
Frequency
31 50 25 21
ns
tW(L)
tW(H)
Minimum Pulse
Width (CLOCK)
4.5 50
15 19 23 ns
ts Minimum Set-up 4.5 50
Time
15 19 23 ns
th Minimum Hold
Time
4.5 50
0 0 0 ns
CIN Input Capacitance
5 10 10 10 pF
COUT Out put
Capacitance
10
pF
CPD (*) Power Dissipation
Capacitance
48
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/8 (per FLIP-FLOP) and CPD
when N pcs of FLIP-FLOP operate, can be gained by following equation: CPD (TOTAL) = 38 + 18 x N (pF)
6/13

6 Page









M74HCT374 pdf, datenblatt
M54/M74HCT374/534
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
12/13
P027A

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