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M74HC374 Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M74HC374
Beschreibung OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 13 Seiten
M74HC374 Datasheet, Funktion
M54/74HC374
M54/74HC534
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
HC374 NON INVERTING - HC534 INVERTING
. HIGH SPEED
fMAX = 77 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN)
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS374/534
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
DESCRIPTION
The M54/74HC374, M54/74HC534, are high speed
CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE
OUTPUTS fabricated with in silicon gate C2MOS
technology. They have the same high speed per-
formance of LSTTL combined with true CMOS low
power comsuption. These8-bit D-type flip-flops are
controlled by a clock input (CK) and an ouput enable
input (OE). On the positive transition of the clock, the
Q outputs will be set to the logic state that were setup
at the D inputs (HC374) or their complements
(HC534).
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
while high level, the outputs will be in a high imped-
ance state. The output control does not affect the in-
ternal operation of flip-flops. That is, the old data can
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting and non-in-
verting outputs. The HC374 and HC574 are identi-
cal, apart from pin layout. The 3-state output
configuration and the wide choice of outline make
bus-organized systems simple. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
PIN CONNECTION (top view)
March 1993
1/13






M74HC374 Datasheet, Funktion
M54/M74HC374/534
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Test Conditions
VCC CL
(V) (pF)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
Value
-40 to 85 oC
74HC
Min. Max.
-55 to 125 oC
54HC
Min. Max.
Unit
tTLH Output Transition 2.0
tTHL Time
4.5 50
25 60 75 90
7 12 15 18 ns
6.0 6 10 13 15
tPLH Propagation
2.0
tPHL Delay Time
4.5 50
(CLOCK - Q, Q) 6.0
45 140 175 210
15 28 35 42 ns
13 24 30 36
2.0
4.5 150
60 190 240 285
20 38 48 57 ns
6.0 17 32 41 48
tPLZ 3 State Output
2.0
39 135 170 205
tPHZ Enable Time
4.5 50 RL = 1 K
13 27
34
41 ns
6.0 11 23 29 35
2.0 54 185 230 280
4.5 150 RL = 1 K
18 37
46
56 ns
6.0 15 31 39 48
fMAX Maximum CLock 2.0
Frequency
4.5 50
6.2 18 5 4.2
31 75 25 21
ns
6.0 37 90 30 25
tW(L)
tW(H)
Minimum Pulse
Width (CLOCK)
2.0
4.5 50
15 75
6 15
95 110
19 22 ns
6.0 6 13 16 19
ts Minimum Set-up 2.0
Time
4.5 50
25 75
6 15
95 110
19 22 ns
6.0 4 13 16 19
th Minimum Hold
Time
2.0
4.5 50
000
0 0 0 ns
6.0 0 0 0
CIN Input Capacitance
5 10
10 10 pF
COUT Out put
Capacitance
10
pF
CPD (*) Power Dissipation
Capacitance
47
pF
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/8 (per FLIP-FLOP) and CPD
when N pcs of FLIP-FLOP operate, can be gained by following equation: CPD (TOTAL) = 30 + 17 x N (pF)
6/13

6 Page









M74HC374 pdf, datenblatt
M54/M74HC374/534
DIM.
A
B
D
d1
d2
E
e
e3
F
G
M
M1
MIN.
9.78
8.89
4.2
7.37
PLCC20 MECHANICAL DATA
mm
TYP.
2.54
0.56
1.27
5.08
0.38
1.27
1.14
MAX.
10.03
9.04
4.57
MIN.
0.385
0.350
0.165
8.38 0.290
0.101
inch
TYP.
0.100
0.022
0.050
0.200
0.015
0.050
0.045
MAX.
0.395
0.356
0.180
0.330
0.004
12/13
P027A

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