PDF M7040N Data sheet ( Hoja de datos )

Número de pieza	M7040N
Descripción	64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
Fabricantes	ST Microelectronics
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M7040N 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE PRELIMINARY DATA FEATURES SUMMARY s 64K DATA ENTRIES IN 72-BIT MODE s TABLE MAY BE PARTITIONED INTO UP TO EIGHT (8) OCTANTS (Data entry width in each octant is configurable as 36, 72, 144, or 288 bits.) s UP TO 100 MILLION SUSTAINED SEARCHES PER SECOND IN 72-BIT and 144-BIT CONFIGURATIONS s UP TO 50 MILLION SEARCHES PER SECOND IN 36-BIT and 288-BIT CONFIGURATIONS s SEARCHES ANY SUB-FIELD IN A SINGLE CYCLE s OFFERS BIT-BY-BIT and GLOBAL MASKING s SYNCHRONOUS, PIPELINED OPERATION s UP TO 31 SEARCH ENGINES CASCADABLE WITHOUT PERFORMANCE DEGRADATION s WHEN CASCADED, THE DATABASE ENTRIES CAN SCALE FROM 496K TO 3968K DEPENDING ON THE WIDTH OF THE ENTRY s GLUELESS INTERFACE TO INDUSTRY- STANDARD SRAMS s SIMPLE HARDWARE INSTRUCTION INTERFACE s IEEE 1149.1 TEST ACCESS PORT s OPERATING SUPPLY VOLTAGES INCLUDE: VDD (Operating Core Supply Voltage) = 1.5V for 66 and 83MSPS; 1.65V for 100MSPS VDDQ (Operating Supply Voltage for I/O) = 2.5 or 3.3V s 388 PBGA, 35mm x 35mm Figure 1. 388-ball PBGA Package 388-ball PBGA 35mm x 35mm May 2002 1/159 1 page M7040N 144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices. . . . . . . . . . . 74 Hit/Miss Assumption (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Hardware Diagram for a Table with 31 Devices (Figure 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Hardware Diagram for a Block of Up to Eight Devices (Figure 53.) . . . . . . . . . . . . . . . . . . . . . . . . 77 x144 Table with 31 Devices (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Timing Diagrams for x144 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 40.). . . . . . . . . . . . . 90 Shift of SSF and SSV from SADR (Table 41.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 288-bit SEARCH on Tables Configured as x288 Using a Single M7040N Device . . . . . . . . . . 90 Hardware Diagram for a Table with One Device (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Timing Diagram for 288-bit SEARCH (One Device) (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 x288 Table with One Device (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Latency of SEARCH from Cycles C and D to SRAM Access Cycle (Table 42.) . . . . . . . . . . . . . . . 93 Shift of SSF and SSV from SADR (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 288-bit SEARCH on Tables x288-configured Using Up to Eight M7040N Devices . . . . . . . . . 94 Hit/Miss Assumption (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Hardware Diagram for a Table with Eight Devices (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 x288 Table with Eight Devices (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Timing Diagrams for x288-configured Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . 98 Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 45.). . . . . . . . 101 Shift of SSF and SSV from SADR (Table 46.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 288-bit Search on Tables Configured as x288 Using Up to 31 M7040N Devices. . . . . . . . . . 101 Hit/Miss Assumption (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Hardware Diagram for a Table with 31 Devices (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Hardware Diagram for a Block of Up to Eight Devices (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . 104 x288 Table with 31 Devices (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Timing Diagrams for x288 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 48.). . . . . . . . 117 Shift of SSF and SSV from SADR (Table 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 MIXED SEARCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Tables Configured with Different Widths Using an M7040N with CFG_L LOW . . . . . . . . . . . . . . 117 Tables Configured to Different Widths using an M7040N with CFG_L HIGH . . . . . . . . . . . . . . . . 117 Timing Diagram for Mixed SEARCH (One Device) (Figure 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Multi-Width Configurations Example (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Searches with CFG_L Set HIGH (Table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LRAM AND LDEV DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Timing Diagram of LEARN: TLSZ = 00 (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) (Figure 91.). . . . . . . . . . . . . 122 Timing Diagram of LEARN on Device 7: TLSZ = 01 (Figure 92.) . . . . . . . . . . . . . . . . . . . . . . . . . 123 Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction (Table 51.) . . . . . . . . 123 5/159 5 Page M7040N MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. Refer also to the STMicroelectronics SURE Program and other rel- evant quality documents. Table 3. Absolute Maximum Ratings Symbol Parameter Value Unit TSTG Storage Temperature (VDD Off) –0 to 70 °C TSLD(1) Lead Solder Temperature for 10 seconds 235 °C VDD VDD Operating Supply Voltage CLK1X = 83MHz CLK1X = 100MHz 1.575 1.733 V V VDDQ VDDQ Voltage for I/O (3.3V) 3.5 V VDDQ VDDQ Voltage for I/O (2.5V) 2.625 V VDDQ VDDQ Voltage for I/O (1.8V) 1.9 V IO Output Current 100 mA Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). 11/159 11 Page

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