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M30620SGP Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer M30620SGP
Beschreibung SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 70 Seiten
M30620SGP Datasheet, Funktion
Description
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/62 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These
single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They
also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, indus-
trial equipment, and other high-speed processing applications.
The M16C/62 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion)
RAM 3K to 20K bytes
• Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=5V)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version
142.9ns (f(XIN)=7MHZ, VCC=3V, with software one-wait) : One-time PROM version
• Supply voltage ..................................... 4.2 to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version
4.5 to 5.5V (f(XIN)=16MHZ, without software wait) : One-time PROM version
2.7 to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait) : One-time PROM version
• Low power consumption ...................... 25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V)
• Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer ...................... 5 output timers + 6 input timers
• Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchro-
nous)
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels)
• D-A converter ....................................... 8 bits X 2 channels
• CRC calculation circuit ......................... 1 circuit
• Watchdog timer .................................... 1 line
• Programmable I/O ............................... 87 lines
_______
• Input port .............................................. 1 line (P85 shared with NMI pin)
• Memory expansion .............................. Available (to 1.2M bytes or 4M bytes)
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) ..................... 11
Reset ............................................................. 14
Processor Mode ............................................ 27
Clock Generating Circuit ............................... 40
Protection ...................................................... 49
Interrupts ....................................................... 50
Watchdog Timer ............................................ 70
DMAC ........................................................... 72
Timer ............................................................. 82
Serial I/O ..................................................... 112
A-D Converter ............................................. 152
D-A Converter ............................................. 162
CRC Calculation Circuit .............................. 164
Programmable I/O Ports ............................. 166
Electrical characteristic ............................... 181
Flash memory version ................................. 234
1






M30620SGP Datasheet, Funktion
Description
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M16C/62 group:
(1) Support for mask ROM version, external ROM version, one-time PROM version, EPROM version, and
Flash memory version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM, one-time PROM, and flash memory versions)
100P6Q-A : Plastic molded QFP(mask ROM, one-time PROM, and flash memory versions)
100D0
: Ceramic LCC (EPROM version)
ROM Size
(Byte)
External
ROM
256K M30624MG-XXXFP/GP
128K
96K
64K
M30620MC-XXXFP/GP
M30622MC-XXXFP/GP
M30620ECFP/GP
M30620MA-XXXFP/GP
M30622MA-XXXFP/GP
M30620M8-XXXFP/GP
M30622M8-XXXFP/GP
32K M30622M4-XXXFP/GP
Mask ROM version One-time PROM version
M30620ECFS
EPROM version
M30624FGFP/GP
M30624FGLFP/GP
M30620SFP/GP
M30622SFP/GP
Flash memory version External ROM version
Figure 1.1.4. ROM expansion
The M16C/62 group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/62 group
November. 1999
Type No
ROM capacity RAM capacity Package type
Remarks
M30622M4-XXXFP
M30622M4-XXXGP
M30620M8-XXXFP
M30620M8-XXXGP
M30622M8-XXXFP
M30622M8-XXXGP
M30620MA-XXXFP
M30620MA-XXXGP
M30622MA-XXXFP
M30622MA-XXXGP
32K byte
64K byte
96K byte
3K byte
10K byte
4K byte
10K byte
5K byte
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
mask ROM version
M30620MC-XXXFP
M30620MC-XXXGP
M30622MC-XXXFP
M30622MC-XXXGP
128K byte
10K byte
5K byte
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
M30624MG-XXXFP
M30624MG-XXXGP
256K byte
20K byte
100P6S-A
100P6Q-A
M30620ECFP
M30620ECGP
128K byte
10K byte
100P6S-A
100P6Q-A
One-time PROM version
M30620ECFS
128K byte
10K byte 100D0
EPROM version (Note)
M30624FGFP
M30624FGGP
M30624FGLFP
M30624FGLGP
M30620SFP
M30620SGP
M30622SFP
M30622SGP
256K byte
256K byte
20K byte
20K byte
10K byte
3K byte
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
Flash memory
5V version
Flash memory
3V version
External ROM version
Note: Do not use the EPROM version for mass production, because it is a tool for program development
(for evaluation).
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M30620SGP pdf, datenblatt
CPU
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
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