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M30620M8A-XXXFP Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer M30620M8A-XXXFP
Beschreibung SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 70 Seiten
M30620M8A-XXXFP Datasheet, Funktion
Description
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/62A group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.
They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications,
industrial equipment, and other high-speed processing applications.
The M16C/62A group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion)
RAM 3K to 20K bytes
• Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=5V)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version
• Supply voltage ..................................... 4.2V to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version
2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version
• Low power consumption ...................... 25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V)
• Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer ...................... 5 output timers + 6 input timers
• Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchro-
nous)
• DMAC .................................................. 2 channels (trigger: 24 sources)
• A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels)
• D-A converter ....................................... 8 bits X 2 channels
• CRC calculation circuit ......................... 1 circuit
• Watchdog timer .................................... 1 line
• Programmable I/O ............................... 87 lines
_______
• Input port .............................................. 1 line (P85 shared with NMI pin)
• Memory expansion .............................. Available (to a maximum of 1M bytes)
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) ..................... 11
Reset ............................................................. 14
Processor Mode ............................................ 21
Clock Generating Circuit ............................... 35
Protection ...................................................... 44
Interrupts ....................................................... 45
Watchdog Timer ............................................ 65
DMAC ........................................................... 67
Timer ............................................................. 77
Serial I/O ..................................................... 107
A-D Converter ............................................. 148
D-A Converter ............................................. 158
CRC Calculation Circuit .............................. 160
Programmable I/O Ports ............................. 162
Electrical characteristic ............................... 173
Flash memory version ................................. 216
1






M30620M8A-XXXFP Datasheet, Funktion
Description
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M16C/62A group:
(1) Support for mask ROM version, external ROM version, and flash memory version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP (mask ROM, and flash memory versions)
100P6Q-A : Plastic molded QFP(mask ROM, and flash memory versions)
ROM Size
(Byte)
External
ROM
256K M30624MGA-XXXFP/GP
128K
96K
64K
M30620MCA-XXXFP/GP
M30622MCA-XXXFP/GP
M30620MAA-XXXFP/GP
M30622MAA-XXXFP/GP
M30620M8A-XXXFP/GP
M30622M8A-XXXFP/GP
32K M30622M4A-XXXFP/GP
Mask ROM version
M30624FGAFP/GP
M30620FCAFP/GP
Flash memory version
M30620SAFP/GP
M30622SAFP/GP
External ROM version
Figure 1.1.4. ROM expansion
The M16C/62A group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/62A group
Type No.
ROM capacity RAM capacity Package type
M30622M4A-XXXFP
M30622M4A-XXXGP
M30620M8A-XXXFP
M30620M8A-XXXGP
M30622M8A-XXXFP
M30622M8A-XXXGP
M30620MAA-XXXFP
M30620MAA-XXXGP
M30622MAA-XXXFP
M30622MAA-XXXGP
M30620MCA-XXXFP
M30620MCA-XXXGP
M30622MCA-XXXFP
M30622MCA-XXXGP
32K byte
64K byte
96K byte
128K byte
3K byte
10K byte
4K byte
10K byte
5K byte
10K byte
5K byte
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
M30624MGA-XXXFP
M30624MGA-XXXGP
256K byte
20K byte
100P6S-A
100P6Q-A
M30620FCAFP
M30620FCAGP
128K byte
10K byte
100P6S-A
100P6Q-A
M30624FGAFP
M30624FGAGP
M30620SAFP
M30620SAGP
256K byte
20K byte
10K byte
100P6S-A
100P6Q-A
100P6S-A
100P6Q-A
M30622SAFP
M30622SAGP
3K byte
100P6S-A
100P6Q-A
****: Under development
March. 2001
Remarks
Mask ROM version
Flash memory
5V version
External ROM
version
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M30620M8A-XXXFP pdf, datenblatt
CPU
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
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