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PDF 74VHCT273AT Data sheet ( Hoja de datos )

Número de pieza 74VHCT273AT
Descripción OCTAL D-TYPE FLIP FLOP WITH CLEAR
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! 74VHCT273AT Hoja de datos, Descripción, Manual

® 74VHCT273A
OCTAL D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 170 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 273
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.9V (Max.)
DESCRIPTION
The 74VHCT273A is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP WITH
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74VHCT273AM
74VHCT273AT
technology.
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs .
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
November 1999
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74VHCT273AT pdf
TEST CIRCUIT
74VHCT273A
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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