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74VHCT20ATTR Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer 74VHCT20ATTR
Beschreibung DUAL 4-INPUT NAND GATE
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 7 Seiten
74VHCT20ATTR Datasheet, Funktion
® 74VHCT20A
DUAL 4-INPUT NAND GATE
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 2 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 20
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74VHCT20A is an advanced high-speed
CMOS DUAL 4-INPUT NAND GATE fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology.
The internal circuit is composed of 3 stages
PRELIMINARY DATA
SOP
TSSOP
PACKAGE
SOP
TSSOP
ORDER CODES
T UB E
T&R
74VHCT20AM 74VHCT20AMTR
74VHCT20ATTR
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 2000
1/7






74VHCT20ATTR Datasheet, Funktion
74VHCT20A
DIM.
A
A1
A2
b
c
D
E
E1
e
K
L
TSSOP14 MECHANICAL DATA
MIN.
0.05
0.85
0.19
0.09
4.9
6.25
4.3
0o
0.50
mm
TYP.
0.10
0.9
5
6.4
4.4
0.65 BSC
4o
0.60
MAX.
1.1
0.15
0.95
0.30
0.20
5.1
6.5
4.48
8o
0.70
MIN.
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0o
0.020
inch
TYP.
0.004
0.354
0.197
0.252
0.173
0.0256 BSC
4o
0.024
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
8o
0.028
A A2
A1 b
e
D
c
KL
E
PIN 1 IDENTIFICATION
1
6/7
E1

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