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PDF 74VHCT174ATTR Data sheet ( Hoja de datos )
| Número de pieza | 74VHCT174ATTR | |
| Descripción | HEX D-TYPE FLIP FLOP WITH CLEAR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® 74VHCT174A
HEX D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX =150 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
s LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHCT174A is an advanced high-speed
CMOS HEX D-TYPE FLIP FLOP WITH CLEAR
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology.
Information signals applied to D inputs are
PRELIMINARY DATA
SOP
TSSOP
PACKAGE
SOP
TSSOP
ORDER CODES
T UB E
T&R
74VHCT174AM 74VHCT174AMTR
74VHCT174ATTR
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independently of the other inputs.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
March 2000
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1 page  
74VHCT174A
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
Test Conditions
V CC
( V)
Value
TA = 25 oC
Min. Typ. Max.
-40 to 85 oC
Min . Max.
Un it
VOLP
VOLV
VIHD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
5.0
5.0
CL = 50 pF
0.3 0.8
-0.8 -0.3
2.0
V
VILD Dynamic Low Voltage
Input (note 1, 3)
5.0
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
5/10
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74VHCT174ATTR.PDF ] | |
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