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PDF MAX9124 Data sheet ( Hoja de datos )
| Número de pieza | MAX9124 | |
| Descripción | Quad LVDS Line Driver | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX9124 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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19-1991; Rev 0; 4/01
EVAALVUAAILTAIOBNLEKIT
Quad LVDS Line Driver
General Description
The MAX9124 quad low-voltage differential signaling
(LVDS) line driver is ideal for applications requiring high
data rates, low power, and low noise. The MAX9124 is
guaranteed to transmit data at speeds up to 800Mbps
(400MHz) over controlled impedance media of approxi-
mately 100Ω. The transmission media may be printed
circuit (PC) board traces, backplanes, or cables.
The MAX9124 accepts four LVTTL/LVCMOS input levels
and translates them to LVDS output signals. Moreover,
the MAX9124 is capable of setting all four outputs to a
high-impedance state through two enable inputs, EN and
EN, thus dropping the device to an ultra-low-power state
of 16mW (typ) during high impedance. The enables are
common to all four transmitters. Outputs conform to the
ANSI TIA/EIA-644 LVDS standard.
The MAX9124 operates from a single +3.3V supply and is
specified for operation from -40°C to +85°C. It is available
in 16-pin TSSOP and SO packages. Refer to the MAX9125/
MAX9126 data sheet for quad LVDS line receivers.
Features
o Pin Compatible with DS90LV031A
o Guaranteed 800Mbps Data Rate
o 250ps Maximum Pulse Skew
o Conforms to TIA/EIA-644 LVDS Standard
o Single +3.3V Supply
o 16-Pin TSSOP and SO Packages
PART
MAX9124EUE
MAX9124ESE
Ordering Information
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
16 SO
Digital Copiers
Laser Printers
Cell Phone Base
Stations
Add/Drop Muxes
Digital Cross-Connects
Applications
DSLAMs
Network
Switches/Routers
Backplane
Interconnect
Clock Distribution
Typical Applications Circuit
LVDS SIGNALS
MAX9124
MAX9126
TX
115Ω
RX
Pin Configuration
TOP VIEW
IN1 1
OUT1+ 2
OUT1- 3
EN 4
OUT2- 5
OUT2+ 6
IN2 7
GND 8
16 VCC
15 IN4
MAX9124
14 OUT4+
13 OUT4-
12 EN
11 OUT3-
10 OUT3+
9 IN3
TSSOP/SO
LVTTL/LVCMOS
DATA INPUT
TX
TX
115Ω
RX
115Ω
RX
LVTTL/LVCMOS
DATA OUTPUT
TX
115Ω
RX
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
* Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
Quad LVDS Line Driver
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the
ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The
LVDS standard uses a lower voltage swing than other
common communication standards, achieving higher
data rates with reduced power consumption while
reducing EMI emissions and system susceptibility to
noise.
The MAX9124 is an 800Mbps quad differential LVDS
driver that is designed for high-speed, point-to-point,
and low-power applications. This device accepts
LVTTL/LVCMOS input levels and translates them to
LVDS output signals.
The MAX9124 generates a 2.5mA to 4.0mA output cur-
rent using a current-steering configuration. This current-
steering approach induces less ground bounce and no
shoot-through current, enhancing noise margin and sys-
tem speed performance. The driver outputs are short-
circuit current limited and enter a high-impedance state
when the device is not powered or is disabled.
The current-steering architecture of the MAX9124
requires a resistive load to terminate the signal and
complete the transmission loop. Because the device
switches current and not voltage, the actual output volt-
age swing is determined by the value of the termination
resistor at the input of an LVDS receiver. Logic states
are determined by the direction of current flow through
the termination resistor. With a typical 3.7mA output
current, the MAX9124 produces an output voltage of
370mV when driving a 100Ω load.
Termination
Because the MAX9124 is a current-steering device, no
output voltage will be generated without a termination
resistor. The termination resistors should match the dif-
ferential impedance of the transmission line. Output
voltage levels depend upon the value of the termination
resistor. The MAX9124 is optimized for point-to-point
interface with 100Ω termination resistors at the receiver
inputs. Termination resistance values may range
between 90Ω and 132Ω, depending on the characteris-
tic impedance of the transmission medium.
Applications Information
Power-Supply Bypassing
Bypass VCC with high-frequency, surface-mount
ceramic 0.1µF and 0.001µF capacitors in parallel as
Table 1. Input/Output Function Table
ENABLES
EN EN
LH
All other combinations
of ENABLE inputs
INPUTS
IN_
X
L
H
OUTPUTS
OUT_+ OUT_ -
ZZ
LH
HL
close to the device as possible, with the smaller valued
capacitor closest to VCC.
Differential Traces
Output trace characteristics affect the performance of
the MAX9124. Use controlled-impedance traces to
match trace impedance to the transmission medium.
Eliminate reflections and ensure that noise couples as
common mode by running the differential trace pairs
close together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have a nominal differential
impedance of 100Ω. To minimize impedance disconti-
nuities, use cables and connectors that have matched
differential impedance.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables, such as twisted
pair, offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
Board Layout
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the LVTTL/LVCMOS
and LVDS signals from each other to prevent coupling.
Chip Information
TRANSISTOR COUNT: 2007
PROCESS: CMOS
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MAX9124.PDF ] | |
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