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PDF MCM72PB8ML4R Data sheet ( Hoja de datos )
| Número de pieza | MCM72PB8ML4R | |
| Descripción | 256K x 72 Bit Burst RAM Multichip Module | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
256K x 72 Bit BurstRAM
Multichip Module
The 256K x 72 multichip module uses four 4M bit synchronous fast static RAMs
designed to provide a burstable, high performance, secondary cache for the
PowerPC™ and other high performance microprocessors. It is organized as
256K words of 72 bits each. This device integrates input registers, an output reg-
ister (MCM72PB8ML only), a 2–bit address counter, and high speed SRAM onto
a single monolithic circuit for reduced parts count in cache data RAM applica-
tions. Synchronous design allows precise cycle control with the use of an exter-
nal clock (K). BiCMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally (burst sequence operates in linear or
interleaved mode dependent upon the state of LBO) and controlled by the burst
address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The eight bytes are designated as “a” through “h”. SBa controls DQa,
SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx
are asserted with SW. All bytes are written if either SGW is asserted or if all SBx
and SW are asserted.
The module can be configured as either a pipelined or flow–through SRAM.
For read cycles, pipelined SRAMs output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (K). Flow–through SRAMs allow output to simply flow freely from
the memory array.
The multichip module operates from a 3.3 V core power supply and all outputs
operate on a separate 2.5 V or 3.3 V power supply. All inputs and outputs are
JEDEC standard JESD8–5 compatible.
• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Option for Pipeline or Flow–Through (Speeds Guaranteed When Module is
Purchased by Appropriate Part Number)
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Single–Cycle Deselect Timing
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• JEDEC BGA Pin Assignment
Order this document
by MCM72FB8ML/D
MCM72FB8ML
MCM72PB8ML
MULTICHIP MODULE
PBGA
CASE 1103B–01
PIN A1
INDICATION
(corner without
fiducial)
TOP VIEW
PIN A1
INDICATION
BOTTOM VIEW
(corner with (Drawings Not to Scale)
fiducial)
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 1
7/30/97
©MMOoTtoOrolRa,OIncL.A19F97AST SRAM
MCM72FB8ML MCM72PB8ML
1
1 page  
PIN DESCRIPTIONS (continued)
Pin Locations
D9, D11, E9, E11, F9, F11, G9 – G11,
H8 – H12, J8 – J12, K8 – K12, L8 – L12,
M8 – M12, N9 – N11, P9, P11, R9, R11,
T9, T11
K7, K13, P10, V7, V13, W7 – W13
Symbol
VSS
Type
Supply Ground.
Description
NC — No Connection: There is no connection to the chip.
TRUTH TABLE (See Notes 1 through 5)
Next Cycle
Address
Used
SE1 SE2 SE3 ADSP ADSC ADV G 3
DQx Write 2, 4
Deselect
None
1
X
X
X
0
X
X High–Z
X
Deselect
None
0X1
0
X
X
X High–Z
X
Deselect
None
0
0
X
0
X
X
X High–Z
X
Deselect
None
XX
1
1
0
X
X High–Z
X
Deselect
Begin Read
Begin Read
None
X0
X
1
0
X
X High–Z
X
External
0
1
0
0
X
X
X High–Z
X5
External
0
1
0
1
0
X
X High–Z READ5
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X X X 1 1 0 0 DQ READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1 X X X 1 0 0 DQ READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ READ
Begin Write
External
0
1
0
1
0
X
X High–Z WRITE
Continue Write
Next
X X X 1 1 0 X High–Z WRITE
Continue Write
Next
1 X X X 1 0 X High–Z WRITE
Suspend Write
Current
X
X
X
1
1
1
X High–Z WRITE
Suspend Write
Current
1
X
X
X
1
1
X High–Z WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X10
X . . . X10
X . . . X11
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X00
X . . . X10
X . . . X11
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
5
5 Page 
VOLTAGE (V)
– 0.5
0
0.8
1.25
1.5
2.3
2.7
2.9
PULL–UP
I (mA) MIN
– 38
– 38
– 38
– 26
– 20
0
0
0
I (mA) MAX
– 105
– 105
– 105
– 83
– 70
– 30
– 10
0
2.9
2.5
2.3
2.1
1.25
0.8
0
0
(a) Pull–Up for 2.5 V I/O Supply
3.6
– 38
CURRENT (mA)
– 105
VOLTAGE (V)
– 0.5
0
1.4
1.65
2.0
3.135
3.6
PULL–UP
I (mA) MIN
– 50
– 50
– 50
– 46
– 35
0
0
I (mA) MAX
– 150
– 150
– 150
– 130
– 101
– 25
0
3.135
2.8
1.65
1.4
0
0
(b) Pull–Up for 3.3 V I/O Supply
– 50 – 100
CURRENT (mA)
– 150
VOLTAGE (V)
– 0.5
0
0.4
0.8
1.25
1.6
2.8
3.2
3.4
PULL–DOWN
I (mA) MIN
0
0
10
20
31
40
40
40
40
I (mA) MAX
0
0
20
40
63
80
80
80
80
VDD
1.6
1.25
0.3
0
0
(c) Pull–Down
40
CURRENT (mA)
Figure 4. Typical Output Buffer Characteristics
80
MOTOROLA FAST SRAM
MCM72FB8ML MCM72PB8ML
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MCM72PB8ML4R.PDF ] | |
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