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PDF MCM69P536C Data sheet ( Hoja de datos )
| Número de pieza | MCM69P536C | |
| Descripción | 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
32K x 36 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM69P536C is a 1M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 32K
words of 36 bits each. This device integrates input registers, an output register,
a 2–bit address counter, and high speed SRAM onto a single monolithic circuit
for reduced parts count in cache data RAM applications. Synchronous design
allows precise cycle control with the use of an external clock (K). BiCMOS cir-
cuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P536C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and
synchronous write enable SW are provided to allow writes to either individual
bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected
byte writes SBx are asserted with SW. All bytes are written if either SGW is
asserted or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P536C operates from a 3.3 V power supply and all inputs and
outputs are LVTTL compatible.
• MCM69P536C–4 = 4 ns Access / 7.5 ns Cycle
MCM69P536C–4.5 = 4.5 ns Access / 8 ns Cycle
MCM69P536C–5 = 5 ns Access / 10 ns Cycle
MCM69P536C–6 = 6 ns Access / 12 ns Cycle
MCM69P536C–7 = 7 ns Access / 13.3 ns Cycle
• Single 3.3 V + 10%, – 5% Power Supply
• ADSP, ADSC, and ADV Burst Control Pins
• Selectable Burst Sequencing Order (Linear/Interleaved)
• Internally Self–Timed Write Cycle
• Byte Write and Global Write Control
• 5 V Tolerant on all Pins (Inputs and I/Os)
• 100–Pin TQFP Package
Order this document
by MCM69P536C/D
MCM69P536C
TQ PACKAGE
TQFP
CASE 983A–01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
REV 3
2/9/98
©MMOoTtoOrolRa,OIncL.A19F98AST SRAM
MCM69P536C
1
1 page  
TRUTH TABLE (See Notes 1 through 4)
Next Cycle
Address
Used
SE1 SE2 SE3 ADSP ADSC ADV G 3
DQx
Write 2, 4
Deselect
None
1 X X X 0 X X High–Z
X
Deselect
None
0X1
0 X X X High–Z
X
Deselect
None 0 0 X 0 X X X High–Z X
Deselect
None X X 1 1 0 X X High–Z X
Deselect
None X 0 X 1 0 X X High–Z X
Begin Read
External
0
1
0
0
X
X
X
High–Z
READ
Begin Read
External
0
1
0
1
0
X
X
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
XXX1 1 0 0
DQ READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1XXX1 0 0
DQ READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ READ
Begin Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Begin Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
Begin Write
External
0
1
0
1
0
X
X
High–Z
WRITE
Continue Write
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X10
X . . . X10
X . . . X11
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External)
2nd Address (Internal)
X . . . X00
X . . . X01
X . . . X01
X . . . X00
X . . . X10
X . . . X11
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Read
Read
Cycle Type
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write All Bytes
SGW
SW
SBa SBb
SBc
SBd
HHXXXX
H L HHHH
HL LHHH
H L H L HH
H L HH L H
H L HHH L
HL L L L L
LXXXXX
MOTOROLA FAST SRAM
MCM69P536C
5
5 Page 
Motorola Memory Prefix
Part Number
ORDERING INFORMATION
(Order by Full Part Number)
MCM 69P536C XX X X
Blank = Trays, R = Tape and Reel
Speed (4 = 4 ns, 4.5 = 4.5 ns, 5 = 5 ns,
6 = 6 ns, 7 = 7 ns)
Package (TQ = TQFP)
Full Part Numbers — MCM69P536CTQ4
MCM69P536CTQ4.5
MCM69P536CTQ5
MCM69P536CTQ6
MCM69P536CTQ7
MCM69P536CTQ4R
MCM69P536CTQ4.5R
MCM69P536CTQ5R
MCM69P536CTQ6R
MCM69P536CTQ7R
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM69P536C
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MCM69P536C.PDF ] | |
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