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PDF MCM67H618A Data sheet ( Hoja de datos )
| Número de pieza | MCM67H618A | |
| Descripción | 64K x 18 Bit BurstRAM Synchronous Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM67H618A/D
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64K x 18 Bit BurstRAM™
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
MCM67H618A
The MCM67H618A is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM67H618A (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information.
• Single 5 V ± 5% Power Supply
• Fast Access Times: 9/10/12 ns Max
• Byte Writeable via Dual Write Enables
• Internal Input Registers (Address, Data, Control)
• Internally Self–Timed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three–State Outputs
• Common Data Inputs and Data Outputs
• 3.3 V I/O Compatible
• High Board Density 52–Lead PLCC Package
• ADSP Disabled with Chip Enable (E) – Supports Address Pipelining
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENT
DQ9
DQ10
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
7 6 5 4 3 2 1 52 51 50 49 48 47
8 46
9 45
10 44
11 43
12 42
13 41
14 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ8
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
PIN NAMES
A0 – A15 . . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock
ADV . . . . . . . . . . . . Burst Address Advance
LW . . . . . . . . . . . . Lower Byte Write Enable
UW . . . . . . . . . . . . Upper Byte Write Enable
ADSC . . . . . . . . . Controller Address Status
ADSP . . . . . . . . . Processor Address Status
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
DQ0 – DQ17 . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
All power supply and ground pins must be
connected for proper operation of the device.
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
5/95
M© OMoTtoOroRla,OInLc.A19F94AST SRAM
MCM67H618A
1
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM67H618A–9 MCM67H618A–10 MCM67H618A–12
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Cycle Time
tKHKH
15
— 16.6 —
20
— ns
Clock Access Time
tKHQV
—
9
—
10
—
12 ns 5
Output Enable to Output Valid
tGLQV
—
5
—
5
—
6 ns
Clock High to Output Active
tKHQX1
6
—
6
—
6
— ns
Clock High to Output Change
tKHQX2
3
—
3
—
3
— ns
Output Enable to Output Active
tGLQX
0
—
0
—
0
— ns
Output Disable to Q High–Z
tGHQZ
—
6
—
7
—
7 ns 6
Clock High to Q High–Z
tKHQZ
3
6
3
7
3
7 ns
Clock High Pulse Width
tKHKL
5
—
5
—
6
— ns
Clock Low Pulse Width
tKLKH
5
—
5
—
6
— ns
Setup Times:
Address tAVKH
2.5
—
2.5
—
2.5
— ns 7
Address Status tADSVKH
Data In tDVKH
Write tWVKH
Address Advance tADVVKH
Chip Enable tEVKH
Hold Times:
Address tKHAX
0.5
—
0.5
—
0.5
— ns 7
Address Status tKHADSX
Data In tKHDX
Write tKHWX
Address Advance tKHADVX
Chip Enable tKHEX
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. A read cycle is defined by UW and LW high or ADSP low for the setup and hold times. A write cycle is defined by LW or UW low and ADSP
high for the setup and hold times.
3. All read and write cycle timings are referenced from K or G.
4. G is a don’t care when UW or LW is sampled low.
5. Maximum access times are guaranteed for all possible i486 and Pentium external bus cycles.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled rather than 100% tested.
At any given voltage and temperature, tKHQZ max is less than tKHQZ1 min for a given device and from device to device.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of K whenever ADSP or
ADSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
K when the chip is enabled. Chip enable must be asserted at each rising edge of clock for the device (when ADSC is low) to remain enabled.
OUTPUT
Z0 = 50 Ω
AC TEST LOADS
RL = 50 Ω
OUTPUT
255 Ω
+5V
480 Ω
5 pF
VL = 1.5 V
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MCM67H618A
5
5 Page 
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
-N- Y BRK
D
-L- 52
LEADS
ACTUAL
-M-
W
B 0.007 (0.180) M T L –M S N S
U 0.007 (0.180) M T L –M S N S
Z
(NOTE 1)
52
1
Z
D
V
A 0.007 (0.180) M T L –M S N S
R 0.007 (0.180) M T L –M S N S
X
VIEW D-D
G1
0.010 (0.250) S T L –M S N S
H 0.007 (0.180) M T L –M S N S
C
E
(NOTE 1)
52
G
G1
0.004 (0.100)
J
-T- SEATING
PLANE
VIEW S
0.010 (0.250) S T L –M S N S
K1
K
F
VIEW S
0.007 (0.180) M T L –M S N S
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.785 0.795 19.94 20.19
B 0.785 0.795 19.94 20.19
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC
1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 — 0.51 —
K 0.025 — 0.64 —
R 0.750 0.756 19.05 19.20
U 0.750 0.756 19.05 19.20
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y — 0.020 — 0.50
Z 2° 10° 2° 10°
G1 0.710 0.730 18.04 18.54
K1 0.040 — 1.02 —
MOTOROLA FAST SRAM
MCM67H618A
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MCM67H618A.PDF ] | |
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