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PDF MCM67D709 Data sheet ( Hoja de datos )
| Número de pieza | MCM67D709 | |
| Descripción | 128K x 9 Bit Synchronous Dual I/O Fast Static RAM | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM67D709/D
128K x 9 Bit Synchronous
Dual I/O Fast Static RAM
MCM67D709
The MCM67D709 is a 1,179,648 bit synchronous static random access
memory organized as 131,072 words of 9 bits, fabricated using Motorola’s
high–performance silicon–gate BiCMOS technology. The device integrates a
128K x 9 SRAM core with advanced peripheral circuitry consisting of address
registers, two sets of input data registers and two sets of output latches. This
device has increased output drive capability supported by multiple power pins.
Asynchronous inputs include the processor output enable (POE) and the
system output enable (SOE).
The address inputs (A0 – A16) are synchronous and are registered on the
falling edge of clock (K). Write enable (W), processor input enable (PIE) and
system input enable (SIE) are registered on the rising edge of clock (K). Writes
to the RAM are self–timed.
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP
have input data registers triggered by the rising edge of the clock. These pins also
have three–state output latches which are transparent during the high
level of the clock and latched during the low level of the clock.
This device has a special feature which allows data to be passed through the
RAM between the system and processor ports in either direction. This streaming
is accomplished by latching in data from one port and asynchronously output
enabling the other port. It is also possible to write to the RAM while streaming.
The MCM67D709’s dual I/Os can be used in x9 separate I/O applications.
Common I/Os PDQ0 – 7, PDQP and SDQ0 – 7, SDQP can be treated as either
inputs (D) or outputs (Q) depending on the state of the control pins. In order to
dedicate PDQ0 – 7, PDQP as data (D) inputs and SDQ0 – 7, SDQP as outputs
(Q), tie SIE and POE high. SOE becomes the asynchronous G for the outputs.
PIE will need to track W for proper write/read operations.
This device is ideally suited for pipelined systems and systems with multiple
data buses and multi–processing systems, where a local processor has a bus
isolated from a common system bus.
• Single 5 V ± 5% Power Supply
• 88110/88410 Compatibility: –16/60 MHz, –20/50 MHz
• Self–Timed Write Cycles
• Clock Controlled Output Latches
• Address and Data Input Registers
• Common Data Inputs and Data Outputs
• Dual I/O for Separate Processor and Memory Buses
• Separate Output Enable Controlled Three–State Outputs
• 3.3 V I/O Compatible
• High Board Density 52 Lead PLCC Package
• Can be used as Separate I/O x9 SRAM
FN PACKAGE
PLASTIC
CASE 778–02
PIN ASSIGNMENTS
A16
A15
PDQ7
SDQ7
VSS
PDQ5
SDQ5
VCC
PDQ3
SDQ3
VSS
PDQ1
SDQ1
7 6 5 4 3 2 1 52 51 50 49 48 47
8 46
9 45
10 44
11 43
12 42
13 41
14 40
15 39
16 38
17 37
18 36
19 35
20 34
21 22 23 24 25 26 27 28 29 30 31 32 33
PIN NAMES
A0 – A16 . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
PIE . . . . . . . . . . . . . Processor Input Enable
SIE . . . . . . . . . . . . . . . System Input Enable
POE . . . . . . . . . . Processor Output Enable
SOE . . . . . . . . . . . . . System Output Enable
PDQ0 – PDQ7 . . . . . . . Processor Data I/O
PDQP . . . . . . . . . . . Processor Data Parity
SDQ0 – SDQ7 . . . . . . . . . System Data I/O
SDQP . . . . . . . . . . . . . System Data Parity
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the
device.
PDQP
SDQP
VSS
PDQ6
SDQ6
VCC
PDQ4
SDQ4
PDQ2
SDQ2
VSS
PDQ0
SDQ0
REV2
5/95
M© OMoTtoOroRla,OInLc.A19F94AST SRAM
MCM67D709
1
1 page  
READ CYCLE (See Note)
tKLKH
tKHKH
tKHKL
K
tKLAX
A0 – A16
An
tAVKL
An + 1
tKHPIEX
tPIEHKH
PIE
tKHSIEX
tSIEHKH
SIE
tKHWX
tWHKH
W
An + 2
POE
tPOELQV
tPOELQX
SOE
PDQ0 – PDQ7, PDQP
SDQ0 – SDQ7, SDQP
tKHQV
tPOEHQZ
tPOEHQX
tSOELQV
Qn
Qn Qn + 1
tKHQX2
tKHQX1
MOTOROLA FAST SRAM
MCM67D709
5
5 Page 
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
-N- Y BRK
D
-L- 52
LEADS
ACTUAL
-M-
W
B 0.007 (0.180) M T L –M S N S
U 0.007 (0.180) M T L –M S N S
Z
(NOTE 1)
52
1
Z
D
V
A 0.007 (0.180) M T L –M S N S
R 0.007 (0.180) M T L –M S N S
X
VIEW D-D
G1
0.010 (0.250) S T L –M S N S
H 0.007 (0.180) M T L –M S N S
C
E
(NOTE 1)
52
G
G1
0.004 (0.100)
J
-T- SEATING
PLANE
VIEW S
0.010 (0.250) S T L –M S N S
K1
K
F
VIEW S
0.007 (0.180) M T L –M S N S
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.785 0.795 19.94 20.19
B 0.785 0.795 19.94 20.19
C 0.165 0.180 4.20 4.57
E 0.090 0.110 2.29 2.79
F 0.013 0.019 0.33 0.48
G 0.050 BSC
1.27 BSC
H 0.026 0.032 0.66 0.81
J 0.020 — 0.51 —
K 0.025 — 0.64 —
R 0.750 0.756 19.05 19.20
U 0.750 0.756 19.05 19.20
V 0.042 0.048 1.07 1.21
W 0.042 0.048 1.07 1.21
X 0.042 0.056 1.07 1.42
Y — 0.020 — 0.50
Z 2° 10° 2° 10°
G1 0.710 0.730 18.04 18.54
K1 0.040 — 1.02 —
MOTOROLA FAST SRAM
MCM67D709
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MCM67D709.PDF ] | |
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