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PDF MCM6729CWJ7R Data sheet ( Hoja de datos )
| Número de pieza | MCM6729CWJ7R | |
| Descripción | 256K x 4 Bit Fast Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256K x 4 Bit Fast Static Random
Access Memory
The MCM6729C is a 1,048,576 bit static random access memory organized
as 262,144 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: 6, 7 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A VCC
A VSS
A
MEMORY
A ROW MATRIX
A
DECODER
512 ROWS x 512 x 4
COLUMNS
A
A
A
DQ COLUMN I/O
INPUT
DATA
COLUMN DECODER
CONTROL
DQ
A A A A AAA A A A
E
W
G
Order this document
by MCM6729C/D
MCM6729C
WJ PACKAGE
400 MIL SOJ
CASE 857A–01
PIN ASSIGNMENT
NC 1
A2
A3
A4
A5
E6
DQ 7
VCC 8
VSS 9
DQ 10
W 11
A 12
A 13
A 14
A 15
NC 16
32 A
31 A
30 A
29 A
28 A
27 G
26 DQ
25 VSS
24 VCC
23 DQ
22 A
21 A
20 A
19 A
18 A
17 NC
PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . No Connection
REV 3
10/9/96
M© OMoTtoOroRla,OInLc.A19F96AST SRAM
MCM6729C
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6729C–6 MCM6729C–7
Parameter
Symbol
Min Max Min Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Address Valid to End of Write,
G High
tAVAV
tAVWL
tAVWH
tAVWH
6 — 7 — ns
0 — 0 — ns
6 — 7 — ns
6 — 7 — ns
3
Write Pulse Width
tWLWH
tWLEH
6 — 7 — ns
Write Pulse Width, G High
tWLWH
tWLEH
6 — 7 — ns
Data Valid to End of Write
tDVWH
3 — 3.5 — ns
Data Hold Time
tWHDX
0 — 0 — ns
Write Low to Data High–Z
tWLQZ
— 3.5 — 3.5 ns 4,5,6
Write High to Output Active
tWHQX
3 — 3 — ns 4,5,6
Write Recovery Time
tWHAX
1 — 1 — ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6729C
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MCM6729CWJ7R.PDF ] | |
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