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PDF MCM6728BWJ8 Data sheet ( Hoja de datos )
| Número de pieza | MCM6728BWJ8 | |
| Descripción | 256K x 4 Bit Fast Static Random Access Memory | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
256K x 4 Bit Fast Static Random
Access Memory
The MCM6728B is a 1,048,576 bit static random access memory organized
as 262,144 words of 4 bits. This device is fabricated using high performance sili-
con–gate BiCMOS technology. Static design eliminates the need for external
clocks or timing strobes.
This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• All Inputs and Outputs Are TTL Compatible
• Three State Outputs
• Fast Access Times: 8, 10, 12 ns
• Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A
A VCC
VSS
A
A MEMORY
A ROW MATRIX
DECODER
512 ROWS x 512 x 4
A COLUMNS
A
A
A
DQ0 COLUMN I/O
INPUT
DATA
COLUMN DECODER
CONTROL
DQ3
A A A A AAA A A
E
W
Order this document
by MCM6728B/D
MCM6728B
WJ PACKAGE
400 MIL SOJ
CASE 810–03
PIN ASSIGNMENT
A1
A2
A3
A4
E5
DQ0 6
VCC 7
VSS 8
DQ1 9
W 10
A 11
A 12
A 13
A 14
28 A
27 A
26 A
25 A
24 A
23 DQ3
22 VSS
21 VCC
20 DQ2
19 A
18 A
17 A
16 A
15 A
PIN NAMES
A0 – A17 . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . Write Enable
DQ0 – DQ3 . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . No Connection
REV 2
5/95
M© OMoTtoOroRla,OInLc.A19F95AST SRAM
MCM6728B
1
1 page  
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
6728B–8
6728B–10
6728B–12
Parameter
Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time
tAVAV
8 — 10 — 12 — ns
3
Address Setup Time
Address Valid to End of Write
tAVWL
tAVWH
0 — 0 — 0 — ns
8 — 9 — 10 — ns
Write Pulse Width
tWLWH, 8 — 9 — 10 — ns
tWLEH
Data Valid to End of Write
tDVWH 4 — 5 — 6 — ns
Data Hold Time
Write Low to Data High–Z
tWHDX 0 — 0 — 0 — ns
tWLQZ 0 4 0 5 0 6 ns 4,5,6
Write High to Output Active
tWHQX 3 — 3 — 3 — ns 4,5,6
Write Recovery Time
tWHAX 0 — 0 — 0 — ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6728B
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM6728BWJ8.PDF ] | |
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