PDF MCF523X Data sheet ( Hoja de datos )

Número de pieza	MCF523X
Descripción	Integrated Microprocessor Hardware Specification
Fabricantes	ETC
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No Preview Available ! Freescale Semiconductor Hardware Specification MCF5235EC Rev. 1.3, 10/2004 MCF523x Integrated Microprocessor Hardware Specification 32-bit Embedded Controller Division The MCF523x is a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring a 16 or 32 channel eTPU, 64 Kbytes of internal SRAM, a 2-bank SDRAM controller, four 32-bit timers with dedicated DMA, a 4 channel DMA controller, up to 2 CAN modules, 3 UARTs and a queued SPI, the MCF523x family has been designed for general purpose industrial control applications. It is also a high-performance upgrade for users of the MC68332. This document provides an overview of the MCF523x microcontroller family, as well as detailed descriptions of the mechanical and electrical characteristics of the devices. The MCF523x family is based on the Version 2 ColdFire reduced instruction set computing (RISC) microarchitecture operating at a core frequency of up to 150 MHz and bus frequency up to 75 MHz. Table of Contents 1 Overview ......................................................... 1 2 Signal Descriptions.......................................... 9 3 Modes of Operation....................................... 14 4 Design Recommendations ............................ 17 5 Mechanicals/Pinouts and Part Numbers ....... 25 6 Preliminary Electrical Characteristics ............ 34 7 Documentation .............................................. 58 1 Overview This 32-bit device's on-chip modules include: Technical Data © Freescale Semiconductor, Inc., 2004. All rights reserved. • Preliminary 1 page Overview 1.3 Features The following section gives a brief overview of this family’s feature set. For more detailed information see the MCF5235 Reference Manual (MCF5235RM). 1.3.1 Feature Overview • Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data path on-chip — Processor core runs at twice the bus frequency — Sixteen general-purpose 32-bit data and address registers — Implements the ColdFire Instruction Set Architecture, ISA_A+, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing — Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms — Illegal instruction decode that allows for 68K emulation support • Enhanced Time Processor Unit (eTPU) — Event triggered VLIW processor timer subsystem — 32 channels — 24-bit timer resolution — 6 Kbyte of code memory and 1.5 Kbyte of data memory — Variable number of parameters allocatable per channel — Double match/capture channels — Angle mode support — DMA and interrupt request support — Nexus Class 1 Debug support • System debug support — Integrated debug supports both ColdFire Debug and Nexus class 1 features on a single port with cross triggering operations for ease of use — Unified programming model including both ColdFire and Nexus debug registers — Real time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging — Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger • On-chip memories — 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache — 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 5 5 Page Signal Descriptions Table 2. MCF523x Signal Information and Muxing (continued) Signal Name GPIO MCF5232 Alternate 1 Alternate 2 Dir.1 160 QFP MCF5232 MCF5233 MCF5234 MCF5235 196 256 256 256 MAPBGA MAPBGA MAPBGA MAPBGA SD_WE PSDRAM5 SD_SCAS PSDRAM4 SD_SRAS PSDRAM3 SD_CKE PSDRAM2 SD_CS[1:0] PSDRAM[1:0] — — — — — IRQ[7:3] IRQ2 IRQ1 PIRQ[7:3] — PIRQ2 PIRQ1 DREQ2 — TPUCH31 TPUCH30 TPUCH29 TPUCH28 TPUCH[27:24] TPUCH23 TPUCH22 TPUCH21 TPUCH20 TPUCH[19:16] TPUCH[15:0] — — — — — — — — — — — ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER ETXCLK ETXEN ETXER ETXD[3:0] — TCRCLK UTPUODIS LTPUODIS PETPU2 PETPU1 PETPU0 — — — EMDIO PFECI2C2 I2C_SDA SDRAM Controller —O 93 K13 L13 L13 L13 —O 92 K12 M15 M15 M15 —O 91 K11 M14 M14 M14 — O 139 E8 C10 C10 C10 — O — L12, L13 N15, M13 N15, M13 N15, M13 External Interrupts Port — I IRQ7=64 N7, M7, L7, R8, T8, N9, R8, T8, N9, R8, T8, N9, IRQ4=65 P8, N8 P9, R9 P9, R9 P9, R9 —I — M8 T9 T9 T9 —I 66 L8 N10 N10 N10 eTPU — — — F3 — F3 — — — F4 — F4 — — — E3 — E3 — — — E4 — E4 — — — D3, D4, C3, — D3, D4, C3, C4 C4 — — — D5 — D5 — — — C5 — C5 — — — D6 — D6 — — — C6 — C6 — — — B6,B5, A5, — B6,B5, A5, B7 B7 — 11, 10, 7:2, E2, E1, D1 F2, E1, E2, F2, E1, E2, F2, E1, E2, 159:154, D2, D3, C1, D1, D2, C1, D1, D2, C1, D1, D2, C1, 152, 151 C2, B1, B2, C2, B1, B2, C2, B1, B2, C2, B1, B2, A2, C3, B3, A2, B3, A3, A2, B3, A3, A2, B3, A3, A3, A4, C4, B4, A4, A6, B4, A4, A6, B4, A4, A6, BR A7 A7 A7 — 12 E3 F1 F1 F1 — — H10 J13 J13 J13 — — G10 J14 J14 J14 FEC U2RXD I/O — — — C7 C7 MCF523x Integrated Microprocessor Hardware Specification, Rev. 1.3 Freescale Semiconductor Preliminary 11 11 Page

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