PDF MC88916DW Data sheet ( Hoja de datos )

Número de pieza	MC88916DW
Descripción	LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Low Skew CMOS PLL Clock Driver With Processor Reset MC88916 The MC88916 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The 88916 comes in two speed grades: 70 and 80MHz. These frequencies correspond to the 2X_Q maximum output frequency. The two grades should be ordered as the MC88916DW70 and MC88916DW80, respectively. LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET • Provides Performance Required to Drive 68030 Microprocessor Family as well as the 33 and 40MHz 68040 Microprocessors • Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input • The Phase Variation From Part–to–Part Between SYNC and the ‘Q’ Outputs Is Less Than 600ps (Derived From the TPD Specification, Which Defines the Part–to–Part Skew) • SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 • Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency. Also a Q (180° Phase Shift) Output Available. • All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible • Test Mode Pin (PLL_EN) Provided for Low Frequency Testing 20 1 DW SUFFIX SOIC PACKAGE CASE 751D–04 The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180° phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency relationships are fixed. In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the RST_OUT(LOCK) pin will remain low. 11/93 © Motorola, Inc. 1995 1 REV 2 1 page MC88916 AC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%) Symbol Parameter Mimimum tRISE/FALL1 All Outputs Rise/Fall Time, All Outputs into a 50Ω Load 0.3 tRISE/FALL1 2X_Q Output Rise/Fall Time into a 20pF Load, With Termination Specified in AppNote 3 0.5 tpulse width(a)1 (Q0, Q1, Q2, Q3) tpulse width(b)1 (2X_Q Output) tPD1,4 SYNC – Q/2 Output Pulse Width Q0, Q1, Q2, Q3 at VCC/2 Output Pulse Width 2X_Q at VCC/2 40–49MHz 50–65MHz 66–80MHz SYNC Input to Q/2 Output Delay (Measured at SYNC and Q/2 Pins) 0.5tcycle – 0.5 0.5tcycle – 1.55 0.5tcycle – 1.05 0.5tcycle – 0.5 –0.75 +1.25 7 tSKEWr1,2 (Rising) tSKEWf1,2 (Falling) tSKEWall1,2 tLOCK3 Output–to–Output Skew Between Outputs Q0–Q2, Q/2 (Rising Edge Only) Output–to–Output Skew Between Outputs Q0–Q2 (Falling Edge Only) Output–to–Output Skew 2X_Q, Q/2, Q0–Q2 Rising Q3 Falling Phase–Lock Acquisition Time, All Outputs to SYNC Input — — — 1 Maximum Unit Condition 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V 0.5tcycle + 0.5 ns 50Ω Load Terminated to VCC/2 (See App Note 3) 0.5tcycle + 1.55 ns 50Ω Load Terminated to 0.5tcycle + 1.05 VCC/2 (See App Note 3) 0.5tcycle + 0.5 –0.15 ns With 1MΩ From RC1 to An VCC (See Application Note 2) +3.25 7 ns With 1MΩ From RC1 to An GND (See Application Note 2) 500 ps Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) 1.0 ns Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) 1.0 ns Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) 10 ms tPHL MR – Q Propagation Delay, MR to Any Output (High–Low) 1.5 13.5 ns Into a 50Ω Load Terminated to VCC/2 (See Timing Diagram in Figure 6) tREC, MR to SYNC6 tW, MR LOW6 tW, RST_IN LOW tPZL Reset Recovery Time rising MR edge to falling SYNC edge Minimum Pulse Width, MR input Low Minimum Pulse Width, RST_IN Low Output Enable Time RST_IN Low to RST_OUT Low 9 5 10 1.5 — ns — ns — ns When in Phase–Lock 16.5 ns See Application Note 5 tPLZ Output Enable Time RST_IN High to RST_OUT High Z 1016 ‘Q’ Cycles 1024 ‘Q’ Cycles ns (508 Q/2 Cycles) (512 Q/2 Cycles) See Application Note 5 1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF. 4. See Application Note 4 for the distribution in time of each output referenced to SYNC. 5. Limits do not meet requirements of the 68040 microprocessor. Refer to the 88920 for a low frequency 68040 clock driver. 6. Specification is valid only when the PLL_EN pin is low. 7. This is a typical specification only, worst case guarantees are not provided. TIMING SOLUTIONS BR1333 — REV 5 5 MOTOROLA 5 Page

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