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74VCX16838 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74VCX16838
Beschreibung Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 7 Seiten
74VCX16838 Datasheet, Funktion
www.DataSheet4U.com
July 1997
Revised July 2000
74VCX16838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CP) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through use of the OE
Pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74VCX16838 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX16838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 and PC133 DIMM module
specifications
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (CP to On)
3.0 ns max for 3.0V to 3.6V VCC
4.0 ns max for 2.3V to 2.7V VCC
8.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
±18 mA @ 2.3V VCC
±6 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Ideal for SDRAM DIMM modules
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16838MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I0I15
O0O15
CP
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Pulse Input
Register Enable Input
© 2000 Fairchild Semiconductor Corporation DS500034
www.fairchildsemi.com






74VCX16838 Datasheet, Funktion
AC Loading and Waveforms
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. Propagation Delay, Pulse Width and trec Waveforms
FIGURE 5. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
Symbol
Vmi
Vmo
VX
VY
3.3V ± 0.3V
1.5V
1.5V
VOL +0.3V
VOH 0.3V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL +0.15V
VOH 0.15V
1.8V ± 0.15V
VCC/2
VCC/2
VOL +0.15V
VOH 0.15V
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