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74VCX16827 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74VCX16827
Beschreibung Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 8 Seiten
74VCX16827 Datasheet, Funktion
www.DataSheet4U.com
March 1998
Revised October 2002
74VCX16827
Low Voltage 20-Bit Buffer/Line Driver with
3.6V Tolerant Inputs and Outputs
General Description
The VCX16827 contains twenty non-inverting buffers with
3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver carrying parity. The device is byte controlled. Each
byte has NOR output enables for maximum control flexibil-
ity.
The 74VCX16827 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX16827 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
2.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16827MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
I0I19
O0O19
Output Enable Input (Active LOW)
Inputs
Outputs
© 2002 Fairchild Semiconductor Corporation DS500131
www.fairchildsemi.com






74VCX16827 Datasheet, Funktion
AC Loading and Waveforms (VCC 3.3V ± 0.3V to 1.8V ± 0.15V)
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
6V at VCC = 3.3V ± 0.3V;
VCC x 2 at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
Vmi
Vmo
VX
VY
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
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