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PDF 74VCX16821 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX16821 | |
| Descripción | Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
Revised October 2004
74VCX16821
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16821 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications.
The 74VCX16821 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX16821 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
3.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Descriptions
74VCX16821MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
CLKn
D0–D19
O0–O19
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
© 2004 Fairchild Semiconductor Corporation DS500130
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 6)
Symbol
Parameter
Conditions
VCC
TA = −40°C to +85°C
Units
Figure
(V) Min Max
Number
fMAX
Maximum Clock Frequency
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
250
200
100
MHz
tPHL Propagation Delay
tPLH
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
80.0
0.8
1.0
1.5
3.5
4.4
8.8
Figures
1, 2
ns
CL = 15 pF, RL = 500Ω
1.5 ± 0.1
1.0
17.6
Figures
7, 8
tPZL
tPZH
Output Enable Time
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.8
3.7
2.5 ± 0.2
1.0
4.7
Figures
1, 3, 4
1.8 ± 0.15
1.5
9.8
ns
CL = 15 pF, RL = 500Ω
1.5 ± 0.1
1.0
19.6
Figures
7, 9, 10
tPLZ
tPHZ
Output Disable Time
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
0.8
3.7
2.5 ± 0.2
1.0
4.2
Figures
1, 3, 4
1.8 ± 0.15
1.5
7.6
ns
CL = 15 pF, RL = 500Ω
1.5 ± 0.1
1.0
15.2
Figures
7, 9, 10
tS Setup Time
CL = 30 pF, RL = 500Ω
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5
1.5
2.5
ns Figure 6
tH Hold Time
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
3.0
1.0
1.0
1.0
ns Figure 6
tW Pulse Width
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
2.0
1.5
1.5
4.0
ns Figure 5
tOSHL
tOSLH
Output to Output Skew
(Note 7)
CL = 15 pF, RL = 500Ω
CL = 30 pF, RL = 500Ω
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
4.0
0.5
0.5
0.75
ns
CL = 15 pF, RL = 500Ω
Note 6: For CL = 50 PF, add approximately 300 ps to the AC maximum specification.
1.5 ± 0.1
1.5
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
5 www.fairchildsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74VCX16821.PDF ] | |
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