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PDF 74VCX162601 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX162601 | |
| Descripción | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in the B-Port Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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April 1998
Revised April 1999
74VCX162601
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V
Tolerant Inputs and Outputs and 26Ω Series Resistors in
the B-Port Outputs
General Description
The VCX162601, 18-bit universal bus transceiver, com-
bines D-type latches and D-type flip-flops to allow data flow
in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. Output-enable OEAB is active-LOW. When OEAB
is HIGH, the outputs are in the HIGH-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
The 74VCX162601 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The VCX162601 is also designed with 26Ω series resistors
in the B-Port outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in B-Port outputs
s tPD (A to B)
3.8 ns max for 3.0V to 3.6V VCC
4.6 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Static Drive (IOH/IOL B outputs)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latchup performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162601MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Pin Names
OEAB, OEBA
LEAB, LEBA
CLKAB, CLKBA
CLKENAB, CLKENBA
A1–A18
B1–B18
Description
Output Enable Inputs (Active LOW)
Latch Enable Inputs
Clock Inputs
Clock Enable Inputs
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500150.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics (Note 11)
TA = −40°C to +85°C, CL = 30 pF, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
VCC = 2.5 ± 0.2V
VCC = 1.8V ± 0.15V
Units
Min Max Min Max Min Max
fMAX
tPHL, tPLH
Maximum Clock Frequency
Propagation Delay
B to A
250 200 100 MHz
0.8 2.9 1.0 3.5 1.5 7.0 ns
tPHL, tPLH Propagation Delay
A to B
0.8 3.8 1.0 4.6 1.5 9.2 ns
tPHL, tPLH Propagation Delay
Clock to A
0.8 3.5 1.0 4.4 1.5 8.8 ns
tPHL, tPLH Propagation Delay
Clock to B
0.8 4.4 1.0 5.5 1.5 9.8 ns
tPHL, tPLH Propagation Delay
LEBA to A
0.8 3.5 1.0 4.4 1.5 8.8 ns
tPHL, tPLH Propagation Delay
LEAB to B
0.8 4.4 1.0 5.8 1.5 9.8 ns
tPZL, tPZH Output Enable Time
OEBA to A
0.8 3.8 1.0 4.9 1.5 9.8 ns
tPZL, tPZH Output Enable Time
OEAB to B
0.8 4.3 1.0 5.9 1.5 9.8 ns
tPLZ, tPHZ Output Disable Time
OEBA to A
0.8 3.7 1.0 4.2 1.5 7.6 ns
tPLZ, tPHZ Output Disable Time
OEAB to B
0.8 4.3 1.0 4.9 1.5 8.8 ns
tS Setup Time
1.5 1.5 2.5
ns
tH Hold Time
1.0 1.0 1.0
ns
tW Pulse Width
1.5 1.5 4.0 ns
tOSHL
tOSLH
Output to Output
Skew (Note 12)
0.5 0.5 0.75
ns
Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
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