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Teilenummer | 74VCX162244 |
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Beschreibung | Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs | |
Hersteller | Fairchild Semiconductor | |
Logo | ||
Gesamt 10 Seiten www.DataSheet4U.com
August 1997
Revised June 2005
74VCX162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistor in Outputs
General Description
The VCX162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX162244 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V. The
74VCX162244 is also designed with 26: series resistors in
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74VCX162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26: series resistors in outputs
s tPD
3.3 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal
s Static Drive (IOH/IOL)
r12 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model ! 2000V
Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162244G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX162244MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS500040
www.fairchildsemi.com
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
Conditions
CL 30 pF, VIH VCC, VIL 0V
VOLV
Quiet Output Dynamic Valley VOL
CL 30 pF, VIH VCC, VIL 0V
VOHV
Quiet Output Dynamic Valley VOH
CL 30 pF, VIH VCC, VIL 0V
Capacitance
VCC
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Symbol
Parameter
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC 1.8, 2.5V or 3.3V, VI 0V or VCC
VI 0V or VCC, VCC 1.8V, 2.5V or 3.3V
VI 0V or VCC, f 10 MHz, VCC 1.8V, 2.5V or 3.3V
TA 25qC
Typical
0.15
0.25
0.35
0.15
0.25
0.35
1.55
2.05
2.65
TA 25qC
Typical
6
7
20
Units
V
V
V
Units
pF
pF
pF
www.fairchildsemi.com
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6 Page | ||
Seiten | Gesamt 10 Seiten | |
PDF Download | [ 74VCX162244 Schematic.PDF ] |
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