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74LVX161284AMTD Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74LVX161284AMTD
Beschreibung Low Voltage IEEE 161284 Translating Transceiver
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 9 Seiten
74LVX161284AMTD Datasheet, Funktion
June 1999
Revised July 2000
74LVX161284A
Low Voltage IEEE 161284 Translating Transceiver
General Description
The LVX161284A contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard, with the exception of output slew rate,
and is intended to be used in an Extended Capabilities Port
mode (ECP). The pinout allows for easy connection from
the Peripheral (A-side) to the Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (± 14 mA) and are connected to a
separate power supply pin (VCCcable) to allow these out-
puts to be driven by a higher supply voltage than the
A-side. The pull-up and pull-down series termination resis-
tance of these outputs on the cable side is optimized to
drive an external cable. In addition, all inputs (except HLH)
and outputs on the cable side contain internal pull-up resis-
tors connected to the VCCcable supply to provide proper
termination and pull-ups for open drain mode.
Outputs on the Peripheral side are standard low-drive
CMOS outputs designed to interface with 3V logic. The DIR
input controls data flow on the A1–A8/B1–B8 transceiver
pins.
Features
s Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
with the exception of output slew rate
s Translation capability allows outputs on the cable side to
interface with 5V signals
s All inputs have hysteresis to provide noise margin
s B and Y output resistance optimized to drive external
cable
s B and Y outputs in high impedance mode during power
down
s Inputs and outputs on cable side have internal pull-up
resistors
s Flow-through pin configuration allows easy interface
between the “Peripheral and Host”
s Replaces the function of two (2) 74ACT1284 devices
Ordering Code
Order Number
Package
Number
Package Description
74LVX161284AMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
HD High Drive Enable Input (Active HIGH)
DIR Direction Control Input
A1A8
B1B8
A9A13
Y9Y13
A14A17
C14C17
PLHIN
PLH
Inputs or Outputs
Inputs or Outputs
Inputs
Outputs
Outputs
Inputs
Peripheral Logic HIGH Input
Peripheral Logic HIGH Output
HLHIN
HLH
Host Logic HIGH Input
Host Logic HIGH Output
© 2000 Fairchild Semiconductor Corporation DS500204
www.fairchildsemi.com






74LVX161284AMTD Datasheet, Funktion
AC Loading and Waveforms
Pulse Generator for all pulses: Rate 1.0 MHz; ZO 50; tf 2.5 ns, tr 2.5 ns.
FIGURE 1. tPHL Test Load and Waveforms
A1A8 to B1B8
A9A13 to Y9Y13
PLHin to PLH
FIGURE 2. tPLH, tpEn, tpDis Test Load and Waveforms
A1A8 to B1B8, A9A13 to Y9Y13
PLHin to PLH, HD to B1B8, Y9Y13, PLH
VMO = 50% VCC
FIGURE 3. tPHL, tPLH Test Load and Waveforms
B1B8 to A1A8, C14C17 to A14A17, HLHin to HLH
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