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74LVT16245B Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74LVT16245B
Beschreibung 3.3 V 16-bit transceiver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 19 Seiten
74LVT16245B Datasheet, Funktion
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
Rev. 10 — 1 March 2012
Product data sheet
1. General description
The 74LVT16245B; 74LVTH16245B is a high-performance BiCMOS product designed for
VCC operation at 3.3 V.
This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. The device features an output enable input (nOE) for easy
cascading and a direction input (nDIR) for direction control.
2. Features and benefits
16-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V






74LVT16245B Datasheet, Funktion
NXP Semiconductors
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
SOT370-1 and
SOT362-1
SOT702-1
1DIR, 2DIR 1, 24
A1, K1
1B0 to 1B7
2, 3, 5, 6, 8, 9, 11, 12
B2, B1, C2, C1, D2,
D1, E2, E1
2B0 to 2B7
13, 14, 16, 17, 19, 20, F1, F2, G1, G2, H1,
22, 23
H2, J1, J2
GND
4, 10, 15, 21, 28, 34, 39, B3, D3, G3, J3, J4,
45 G4, D4, B4
VCC
1OE, 2OE
7, 18, 31, 42
48, 25
C3, H3, H4, C4
A6, K6
2A0 to 2A7
1A0 to 1A7
n.c.
36, 35, 33, 32, 30, 29,
27, 26
47, 46, 44, 43, 41, 40,
38, 37
-
F6, F5, G6, G5, H6,
H5, J6, J5
B5, B6, C5, C6, D5,
D6, E5, E6
A2, A3, A4, A5,
K2, K3, K4, K5
SOT1134-2
Description
A30, A13
direction control input
B20, A31, D5, D1, A2, data input/output
B2, B3, A5
A6, B5, B6, A9, D2,
D6, A12, B8
data input/output
A32, A3, A8, A11, A16, ground (0 V)
A19, A24, A27
A1, A10, A17, A26 supply voltage
A29, A14
output enable input (active
LOW)
A21, B13, B12, A18, data input/output
D3, D7, A15, B10
B18, A28, D8, D4,
data input/output
A25, B16, B15, A22
A4, A7, A20, A23, B1, not connected
B4, B7, B9, B11, B14,
B17, B19
6. Functional description
6.1 Function table
Table 3.
Control
nOE
L
L
H
Function table [1]
nDIR
L
H
X
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Input/output
nAn
output nAn = nBn
input
Z
nBn
input
output nBn = nAn
Z
74LVT_LVTH16245B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 1 March 2012
© NXP B.V. 2012. All rights reserved.
6 of 19

6 Page









74LVT16245B pdf, datenblatt
NXP Semiconductors
74LVT16245B; 74LVTH16245B
3.3 V 16-bit transceiver; 3-state
12. Package outline
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
y
Z
48
pin 1 index
1
e
c
25
EA
X
HE v M A
24
wM
bp
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1) E (1)
e
HE
L
Lp
Q
v
w
y Z (1) θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22 16.00
0.13 15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25 0.18
0.1
0.85
0.40
8o
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
IEC
REFERENCES
JEDEC
JEITA
MO-118
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 9. Package outline SOT370-1 (SSOP48)
74LVT_LVTH16245B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 1 March 2012
© NXP B.V. 2012. All rights reserved.
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