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PDF 74LVT162374DGG Data sheet ( Hoja de datos )
| Número de pieza | 74LVT162374DGG | |
| Descripción | 3.3 V 16-bit edge-triggered D-type flip-flop with 30 OHM termination resistors; 3-state | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω
termination resistors; 3-state
Rev. 03 — 17 January 2005
Product data sheet
1. General description
The 74LVT162374 is a high performance BiCMOS product designed for VCC operation at
3.3 V.
The 74LVT162374 is designed with 30 Ω series resistance in both the HIGH and LOW
states of the output. This design reduces line noise in applications such as memory
address drivers, clock drivers, and bus receivers/transmitters.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels
set up at the D inputs.
2. Features
s 16-bit edge-triggered flip-flop
s 3-state buffers
s Output capability: +12 mA and −12 mA
s TTL input and output switching levels
s Input and output interface capability to systems at 5 V supply
s Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s Outputs include series resistance of 30 Ω making external resistors unnecessary
s Power-up reset
s Power-up 3-state
s No bus current loading when output is tied to 5 V bus
s Latch-up protection exceeds 500 mA per JESD78
s ESD protection:
x MIL STD 883 method 3015: exceeds 2000 V
x Machine model: exceeds 200 V
1 page  
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
6.2 Pin description
Table 3:
Symbol
1OE
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
2CP
2D7
2D6
GND
2D5
2D4
VCC
2D3
2D2
GND
2D1
2D0
1D7
1D6
GND
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
output enable input (active LOW)
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
output enable input (active LOW)
clock pulse input (active rising edge)
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
data input
ground (0 V)
data input
data input
data input
data input
ground (0 V)
9397 750 14401
Product data sheet
Rev. 03 — 17 January 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 17
5 Page 
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
nDn
nCP
VM VM
tsu(H) th(H)
VM
VM VM
tsu(L) th(L)
VM
2.7 V
0V
2.7 V
0V
001aac376
VM = 1.5 V; VI = GND to 3.0 V.
Remark: The shaded areas indicate when the input is permitted to change for predictable
output performance.
Fig 9. Data set-up and hold times
VI
negative
pulse
0V
90 %
VI
positive
pulse
0V
10 %
tW
VM
10 %
tTHL(tf)
tTLH(tr)
90 %
VM
tW
VM = 1.5 V.
a. Input pulse definition
90 %
VM
tTLH(tr)
tTHL(tf)
VM
10 %
001aac221
VCC
PULSE
GENERATOR
VI
D.U.T.
VO
RT
VEXT
RL
CL RL
mna616
Test data is given in Table 10.
Definitions:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
b. Test circuit
Fig 10. Load circuitry for switching times
9397 750 14401
Product data sheet
Rev. 03 — 17 January 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 17
11 Page | ||
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| PDF Descargar | [ Datasheet 74LVT162374DGG.PDF ] | |
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