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74LVQ273SC Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer 74LVQ273SC
Beschreibung Low Voltage Octal D-Type Flip-Flop
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 6 Seiten
74LVQ273SC Datasheet, Funktion
April 1998
74LVQ273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVQ273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ273SC
74LVQ273SJ
74LVQ273QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
20-Lead Shrink Molded Small Outline Package, SOIC EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011358-1
IEEE/IEC
DS011358-2
DS011358-3
Pin Descriptions
Pin Names
D0– D7
MR
CP
Q0– Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
© 1998 Fairchild Semiconductor Corporation DS011358
www.fairchildsemi.com






74LVQ273SC Datasheet, Funktion
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC
(also known as QSOP)
Package Number MQA20
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys- 2. A critical component in any component of a life support
tems which, (a) are intended for surgical implant into
device or system whose failure to perform can be rea-
the body, or (b) support or sustain life, and (c) whose
sonably expected to cause the failure of the life support
failure to perform when properly used in accordance
device or system, or to affect its safety or effectiveness.
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Corporation
Americas
Customer Response Center
Tel: 1-888-522-5372
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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