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PDF MG113P Data sheet ( Hoja de datos )

Número de pieza MG113P
Descripción 0.25m Sea of Gates and Customer Structured Arrays
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No Preview Available ! MG113P Hoja de datos, Descripción, Manual

DATA SHEET
OKI
ASIC
PRODUCTS
MG113P/114P/115P/73P/74P/75P
0.25µm Sea of Gates and
Customer Structured Arrays
November 1999

1 page




MG113P pdf
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG113P/114P/115P/73P/74P/75P s
MG113P/114P/115P/73P/74P/75P FAMILY LISTING
60µm Staggered PAD products
SOG Base Array
MG11xP14
MG11xP18
MG11xP22
MG11xP28
EA Base Array
MG7xPB02
MG7xPB04
MG7xPB06
MG7xPB08
MG7xPB10
MG7xPB12
MG7xPB14
MG7xPB16
MG7xPB18
MG7xPB20
MG7xPB22
MG7xPB24
MG7xPB26
MG7xPB28
MG7xPB30
MG7xPB32
MG7xPB34
MG7xPB36
MG7xPB38
MG7xPB40
MG7xPB42
No. of
Pads
68
108
148
188
228
268
308
348
388
428
468
508
548
588
628
668
708
748
788
828
868
No. of
Rows
84
144
204
264
324
384
444
504
564
624
684
744
804
864
924
984
1,044
1,104
1,164
1,224
1,284
No. of
Columns
280
480
680
880
1,080
1,280
1,480
1,680
1,880
2,080
2,280
2,480
2,680
2,880
3,080
3,280
3,480
3,680
3,880
4,080
4,280
No. of
Raw
Gates
23,520
69,120
138,720
232,320
349,920
491,520
657,120
846,720
1,060,320
1,297,920
1,559,920
1,845,120
2,154,720
2,488,320
2,845,920
3,227,520
3,633,120
4,062,720
4,516,320
4,993,920
5,495,520
MG113P/73P
Family 3LM
Usable Gates
387,701
572,573
732,974
1,094,861
MG114P/74P
Family 4LM
Usable Gates
22,344
65,664
131,784
218,381
311,429
412,877
519,125
635,040
763,430
882,586
982,498
1,107,072
1,249,738
1,393,459
1,536,797
1,678,310
1,816,560
1,950,106
2,077,507
2,197,325
2,308,118
MG115P/75P
Family 5LM
Usable Gates
22,344
65,664
131,784
220,704
332,424
466,944
611,122
745,114
901,272
1,025,357
1,154,045
1,310,035
1,465,210
1,642,291
1,821,389
2,001,062
2,179,872
2,356,378
2,529,139
2,696,717
2,857,670
ARRAY ARCHITECTURE
The primary components of a 0.25µm MG113P/114P/115P circuit include:
• I/O base cells
• 60µm pad pitch
• Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O)
• VDD and VSS pads dedicated to wafer probing
• Separate power bus for output buffers
• Separate power bus for internal core logic and input buffers
• Core base cells containing N-channel and P-channel pairs, arranged in column of gates
• Isolated gate structure for reduced input capacitance and increased routing flexibility
• Innovative 4-transistor core cell architecture, licensed from In-Chip Systems, Inc
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads
per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC)
and output drive transistors (VDDO and VSSO).
Oki Semiconductor
3

5 Page





MG113P arduino
––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– s MG113P/114P/115P/73P/74P/75P s
DC Characteristics (VDD Core = 2.25 to 2.75 V, VDD I/O = 2.25 to 2.75 V, VSS = 0 V, Tj = -40° to +125°C)
Parameter
Symbol
Conditions
Rated Value
Min. Typ. [1] Max.
Unit
High-level input voltage
Low-level input voltage
TTL- level Schmitt
Trigger input buffer
Threshold voltage
High-level output voltage (Output buffer)
VIH
VIL
Vt+
Vt-
Vt
VOH
Low-level output voltage (Output buffer)
VOL
High-level input current (Input buffer)
Low-level input current (Normal input buffer)
IIH
IIL
3-state output leakage current
(Normal input buffer)
Stand-by current [2]
IOZH
IOZL
IDDQ
TTL input (normal), VDD=VDD I/O
TTL input (normal)
1.7
-0.3
- VDD + 0.3
- 0.7
TTL input (normal)
- - 1.7
0.6 -
-
Vt+ - Vt-
- 0.4 -
IOH = -100 µA, VDD=VDD I/O
VDD - 0.2
-
-
IOH = -0.5, -1, -2, -3, -4, -6, -12 mA 1.95
-
-
IOL = 100 µA
- - 0.2
IOL = -0.5, 1, 2, 3, 4, 6, 12 mA
-
- 0.45
VIH = VDD
-50 - 50
VIL = VSS
-50 - 50
VIL = VSS (3-kpull-up)
- -0.8 -
VOH = VDD
-50 - 50
VOL = VSS
-50 - 50
VOL = VSS (3-kpull-up)
- -0.8 -
Output open, VIH = VDD, VIL = VSS
Design Dependent
V
µA
mA
µA
mA
µA
1. Typical condition is VDD I/O = 2.5 V, VDD Core = 2.5 V, and Tj = 25°C for a typical process.
2. RAM/ROM should be in powerdown mode.
Oki Semiconductor
9

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