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PDF MAX5184 Data sheet ( Hoja de datos )

Número de pieza MAX5184
Descripción 10-Bit / 40MHz / Current/Voltage-Output DACs
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX5184 Hoja de datos, Descripción, Manual

19-1579; Rev 0; 12/99
10-Bit, 40MHz, Current/Voltage-Output DACs
General Description
The MAX5181 is a 10-bit, current-output digital-to-ana-
log converter (DAC) designed for superior performance
in signal reconstruction or arbitrary waveform genera-
tion applications requiring analog signal reconstruction
with low distortion and low-power operation. The
MAX5184 provides equal specifications, with on-chip
precision resistors for voltage-output operation. The
MAX5181/MAX5184 are designed for a 10pVs glitch
operation to minimize unwanted spurious signal com-
ponents at the output. An on-board +1.2V bandgap cir-
cuit provides a well-regulated, low-noise reference that
can be disabled for external reference operation.
The devices are designed to provide a high level of sig-
nal integrity for the least amount of power dissipation.
They operate from a single +2.7V to +3.3V supply.
Additionally, these DACs have three modes of opera-
tion: normal, low-power standby, and full shutdown,
which provides the lowest possible power dissipation
with a 1µA max shutdown current. A fast wake-up time
(0.5µs) from standby mode to full DAC operation facili-
tates power conservation by activating the DAC only
when required.
The MAX5181/MAX5184 are available in 24-pin QSOP
packages and are specified for the extended (-40°C to
+85°C) temperature range. For lower resolution, 8-bit
versions, refer to the MAX5187/MAX5190 data sheet.
Features
o +2.7V to +3.3V Single-Supply Operation
o Wide Spurious-Free Dynamic Range: 70dB
at fOUT = 2.2MHz
o Fully Differential Output
o Low-Current Standby or Full Shutdown Modes
o Internal +1.2V, Low-Noise Bandgap Reference
o Small 24-Pin QSOP Package
PART
MAX5181BEEG
MAX5184BEEG
Ordering Information
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 QSOP
24 QSOP
Pin Configuration
Applications
Signal Reconstruction
Arbitrary Waveform Generators (AWGs)
Direct Digital Synthesis
Imaging Applications
TOP VIEW
CREF 1
OUTP 2
OUTN 3
AGND 4
AVDD 5
DACEN 6
PD 7
CS 8
CLK 9
REN 10
DO 11
D1 12
MAX5181
MAX5184
QSOP
24 REFO
23 REFR
22 DGND
21 DVDD
20 D9
19 D8
18 D7
17 D6
16 D5
15 D4
14 D3
13 D2
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.

1 page




MAX5184 pdf
10-Bit, 40MHz, Current/Voltage-Output DACs
Typical Operating Characteristics (continued)
(AVDD = DVDD = +3V, AGND = DGND = 0, IFS = 1mA, 400differential output, CL = 5pF, TA = +25°C, unless otherwise noted.)
SHUTDOWN CURRENT vs.
TEMPERATURE
0.13
0.11
0.09
MAX5181
0.07
MAX5184
0.05
0.03
-40
4.0
-15 10 35
60
TEMPERATURE (°C)
OUTPUT CURRENT vs.
REFERENCE CURRENT
85
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.28
1.27
1.26
MAX5184
1.25 MAX5181
1.24
1.23
2.5
3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
DYNAMIC RESPONSE RISE TIME
MAX5181/4toc14
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1.28
1.27
1.26
MAX5181
1.25
MAX5184
1.24
1.23
-40
-15 10 35
60
TEMPERATURE (°C)
85
DYNAMIC RESPONSE FALL TIME
MAX5181/4toc15
3.0
OUTP
OUTP
150mV/
150mV/
div div
2.0
1.0
0
0
OUTN
150mV/
div
OUTN
150mV/
div
100 200 300 400
REFERENCE CURRENT (µA)
500
500ns/div
SETTLING TIME
MAX5181/4toc16
0
-10
-20
FFT PLOT
fOUT = 2.2MHz
fCLK = 40MHz
OUTN
100mV/
div
-30
-40
-50
-60
-70
-80
OUTP -90
100mV/
div
-100
-110
12.5ns/div
-120
0 2 4 6 8 10 12 14 16 18 20
OUTPUT FREQUENCY (MHz)
500ns/div
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
100
90
80
70
60
50
40
10 15 20 25 30 35 40 45 50 55 60
CLOCK FREQUENCY (MHz)
_______________________________________________________________________________________ 5

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MAX5184 arduino
10-Bit, 40MHz, Current/Voltage-Output DACs
tCLK
CLK
tCL tCH
D0D9
OUT
N-1
tDS
Figure 4. Timing Diagram
N-1
N
tDH
N
N+1
N+1
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
THD = 20 log
(V22 + V32 + V42 + V52)
V1
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion com-
ponent.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5181. The differential
voltage across OUTP and OUTN is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
I/Q Reconstruction
in a QAM Application
The low-distortion performance of two MAX5181/
MAX5184s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) archi-
tectures where two separate buses carry the I and Q
data. A QAM signal is both amplitude (AM) and phase
modulated, created by summing two independently
modulated carriers of identical frequency but different
phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5181/MAX5184 may be used to reconstruct the
analog I and Q components.
______________________________________________________________________________________ 11

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