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PDF MAX5156 Data sheet ( Hoja de datos )
| Número de pieza | MAX5156 | |
| Descripción | Low-Power / Dual / 12-Bit Voltage-Output DACs with Configurable Outputs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX5156 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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19-1317; Rev 1; 12/97
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs
_______________General Description
The MAX5156/MAX5157 low-power, serial, voltage-out-
put, dual 12-bit digital-to-analog converters (DACs)
consume only 500µA from a single +5V (MAX5156) or
+3V (MAX5157) supply. These devices feature Rail-to-
Rail® output swing and are available in space-saving
16-pin QSOP and DIP packages. Access to the invert-
ing input allows for specific gain configurations, remote
sensing, and high output current capability, making
these devices ideally suited for industrial process con-
trols. These devices are also well suited for digitally
programmable (4–20mA) current loops.
The 3-wire serial interface is SPI™/QSPI™ and
Microwire™ compatible. Each DAC has a double-
buffered input organized as an input register followed
by a DAC register, which allows the input and DAC reg-
isters to be updated independently or simultaneously.
Additional features include a programmable shutdown
(2µA), hardware-shutdown lockout, a separate voltage
reference for each DAC, power-on reset, and an active-
low clear input (CL) that resets all registers and DACs to
zero. The MAX5156/MAX5157 provide a programmable
logic output pin for added functionality, and a serial-
data output pin for daisy chaining.
________________________Applications
Industrial Process Control
Digital Offset and Gain
Adjustment
Remote Industrial Controls
Motion Control
Digitally Programmable
4–20mA Current Loops
Automatic Test Equipment
____________________________Features
o 12-Bit Dual DAC with Configurable Output
Amplifier
o Single-Supply Operation: +5V (MAX5156)
+3V (MAX5157)
o Rail-to-Rail Output Swing
o Low Quiescent Current: 500µA (normal operation)
2µA (shutdown mode)
o Power-On Reset Clears DAC Outputs to Zero
o SPI/QSPI and Microwire Compatible
o Space-Saving 16-Pin QSOP Package
_______________Ordering Information
PART
TEMP. RANGE
MAX5156ACPE
MAX5156BCPE
MAX5156ACEE
MAX5156BCEE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
INL
(LSB)
16 Plastic DIP ±1/2
16 Plastic DIP ±1
16 QSOP
±1/2
16 QSOP
±1
Ordering Information continued at end of data sheet.
Pin Configuration appears at end of data sheet.
_________________________________________________________Functional Diagram
DOUT CL
PDL
DGND AGND VDD
REFA
16-BIT
SHIFT
REGISTER
SR
CONTROL
DECODE
CONTROL
LOGIC
OUTPUT
INPUT
REG A
INPUT
REG B
DAC
REG A
DAC A
MAX5156
MAX5157
DAC
REG B
DAC B
OUTA
FBA
OUTB
FBB
CS DIN SCLK UPO
REFB
Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
1 page  
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs
ELECTRICAL CHARACTERISTICS—MAX5157 (continued)
(VDD = +2.7V to +3.6V, VREFA = VREFB = 1.25V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25°C, output buffer connected in unity-gain configuration (Figure 9).)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
Power-Supply Current in
Shutdown
VDD
IDD (Note 7)
IDD(SHDN) (Note 7)
2.7 3.6 V
0.5 0.6 mA
1 8 µA
Reference Current in
Shutdown
±1 µA
TIMING CHARACTERISTICS
SCLK Clock Period
tCP (Note 4)
SCLK Pulse Width High
tCH
SCLK Pulse Width Low
tCL
CS Fall to SCLK Rise Setup
Time
tCSS
100 ns
40 ns
40 ns
40 ns
SCLK Rise to CS Rise Hold
Time
tCHS
0 ns
DIN Setup Time
DIN Hold Time
SCLK Rise to DOUT Valid
Propagation Delay
tDS
tDH
tDO1
CLOAD = 200pF
50 ns
0 ns
120 ns
SCLK Fall to DOUT Valid
Propagation Delay
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
tDO2
tCS0
tCS1
tCSW
CLOAD = 200pF
120 ns
10 ns
40 ns
100 ns
Note 5: Accuracy is specified from code 20 to code 4095.
Note 6: Accuracy is better than 1LSB for VOUT greater than 6mV and less than VDD - 100mV. Guaranteed by PSRR test at the end
points.
Note 7: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.
_______________________________________________________________________________________ 5
5 Page 
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Configurable Outputs
SCLK
MAX5156 DIN
MAX5157
CS
SK
MICROWIRE
SO PORT
I/O
Figure 2. Connections for Microwire
VCC
DIN
MAX5156 SCLK
MAX5157
CS
SS
MOSI
SPI/QSPI
SCK PORT
I/O
CPOL = 0, CPHA = 0
Figure 3. Connections for SPI/QSPI
MSB...................................................................................LSB
16 Bits of Serial Data
Address Bits
Control Bits
MSB...DataBits...LSB
Sub
Bit
A0 C1, C0
1 Address/2 Control Bits
D11.......................D0 S0
12 Data Bits
0
Figure 4. Serial-Data Format
The MAX5156/MAX5157’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated, and the state of the registers
when exiting shutdown. The 3-bit address/control
determines the following:
• registers to be updated
• clock edge on which data is clocked out via the seri-
al data output (DOUT)
• state of the user-programmable logic output
• configuration of the device after shutdown
The general timing diagram in Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
Serial Data Output (DOUT)
DOUT is the internal shift register’s output. It allows for
daisy-chaining and data readback. The MAX5156/
MAX5157 can be programmed to shift data out of
DOUT on SCLK’s falling edge (Mode 0) or rising edge
(Mode 1). Mode 0 provides a lag of 16 clock cycles,
which maintains compatibility with SPI/QSPI and
Microwire interfaces. In Mode 1, the output data lags
15.5 clock cycles. On power-up, the device defaults to
Mode 0.
User-Programmable Logic Output (UPO)
UPO allows an external device to be controlled through
the MAX5156/MAX5157 serial interface (Table 1), there-
by reducing the number of microcontroller I/O pins
required. On power-up, UPO is low.
Power-Down Lockout Input (PDL)
PDL disables software shutdown when low. When in
shutdown, transitioning PDL from high to low wakes up
the part with the output set to the state prior to shut-
down. PDL can also be used to asynchronously wake
up the device.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX5156.PDF ] | |
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