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PDF MAX500 Data sheet ( Hoja de datos )
| Número de pieza | MAX500 | |
| Descripción | CMOS / Quad / Serial-Interface 8-Bit DAC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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19-1016; Rev 2; 2/96
CMOS, Quad, Serial-Interface
8-Bit DAC
_______________General Description
The MAX500 is a quad, 8-bit, voltage-output digital-to-
analog converter (DAC) with a cascadable serial inter-
face. The IC includes four output buffer amplifiers and
input logic for an easy-to-use, two- or three-wire serial
interface. In a system with several MAX500s, only one
serial data line is required to load all the DACs by cas-
cading them. The MAX500 contains double-buffered
logic and a 10-bit shift register that allows all four DACs
to be updated simultaneously using one control signal.
There are three reference inputs so the range of two of
the DACs can be independently set while the other two
DACs track each other.
The MAX500 achieves 8-bit performance over the full
operating temperature range without external trimming.
________________________Applications
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
Industrial Process Control
Arbitrary Function Generators
Automatic Test Equipment
________________Functional Diagram
AGND
VREFC
SRO DGND VSS VDD LDAC VREFA/B VREFD
INPUT
REG A
DAC
REG A
DAC A
VOUTA
____________________________Features
o Buffered Voltage Outputs
o Double-Buffered Digital Inputs
o Microprocessor and TTL/CMOS Compatible
o Requires No External Adjustments
o Two- or Three-Wire Cascadable Serial Interface
o 16-Pin DIP/SO Package and 20-Pin LCC
o Operates from Single or Dual Supplies
______________Ordering Information
PART TEMP. RANGE PIN-PACKAGE ERROR (LSB)
MAX500ACPE 0°C to +70°C 16 Plastic DIP
±1
MAX500BCPE 0°C to +70°C 16 Plastic DIP
±2
MAX500ACWE 0°C to +70°C
MAX500BCWE 0°C to +70°C
MAX500BC/D 0°C to +70°C
MAX500AEPE -40°C to +85°C
16 Wide SO
16 Wide SO
Dice*
16 Plastic DIP
±1
±2
±2
±1
MAX500BEPE -40°C to +85°C
MAX500AEWE -40°C to +85°C
MAX500BEWE -40°C to +85°C
MAX500AEJE -40°C to +85°C
16 Plastic DIP
16 Wide SO
16 Wide SO
16 CERDIP
±2
±1
±2
±1
MAX500BEJE -40°C to +85°C
MAX500AMJE -55°C to +125°C
MAX500BMJE -55°C to +125°C
MAX500AMLP -55°C to +125°C
16 CERDIP
16 CERDIP
16 CERDIP
20 LCC
±2
±1
±2
±1
MAX500BMLP -55°C to +125°C 20 LCC
±2
*Contact factory for dice specifications.
_________________Pin Configurations
10/11-
BIT
SHIFT
REGISTER
CONTROL
LOGIC
LOAD SDA
SCL
INPUT
REG B
DAC
REG B
DAC B
INPUT
REG C
DAC
REG C
DAC C
INPUT
REG D
DAC
REG D
DAC D
MAX500
VOUTB
VOUTC
VOUTD
TOP VIEW
VOUTB 1
VOUTA 2
VSS 3
VREFA/B 4
AGND 5
DGND 6
LDAC 7
SDA 8
MAX500
16 VOUTC
15 VOUTD
14 VDD
13 VREFC
12 VREFD
11 SRO
10 SCL
9 LOAD
DIP/SO
Pin Configurations continued on last page.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
CMOS, Quad, Serial-Interface
8-Bit DAC
____________________________Typical Operating Characteristics (continued)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
16
VSS = -5V
14
12 RO ≅ 200Ω
10 VSS = 0V
8
6
4
2
0
0
2 4 6 8 10
VOUT (V)
12
10
8
6
4
2
0
-2
-4
-6
-55
SUPPLY CURRENT
vs. TEMPERATURE
IDD
ISS
-25 0 25 50 75 100 125
TEMPERATURE (°C)
ZERO-CODE ERROR
vs. TEMPERATURE
2.0
1.5 VOUTA
1.0
0.5 VOUTB
0.0
VOUTC
-0.5
-1.0 VOUTD
-1.5
VSS = -5V
-2.0
-55 -25 0
25 50
75
TEMPERATURE (°C)
100 125
_______________Detailed Description
The MAX500 has four matched voltage-output digital-to-
analog converters (DACs). The DACs are “inverted”
R-2R ladder networks which convert 8 digital bits into
equivalent analog output voltages in proportion to the
applied reference voltage(s). Two DACs in the MAX500
have a separate reference input while the other two
DACs share one reference input. A simplified circuit
diagram of one of the four DACs is provided in Figure 1.
R
…
R
R
VOUT
2R
2R
2R 2R 2R
DB0 DB5 DB6
VREF DB0
AGND
DB5
…
…
DB6
DB7
Figure 1. Simplified DAC Circuit Diagram
DB7
VREF Input
The voltage at the VREF pins (pins 4, 12, and 13) sets
the full-scale output of the DAC. The input impedance
of the VREF inputs is code dependent. The lowest
value, approximately 11kΩ (5.5kΩ for VREFA/B), occurs
when the input code is 01010101. The maximum value
of infinity occurs when the input code is 00000000.
Because the input resistance at VREF is code depen-
dent, the DAC’s reference sources should have an out-
put impedance of no more than 20Ω (no more than
10Ω for VREFA/B). The input capacitance at VREF is
also code dependent and typically varies from 15pF to
35pF (30pF to 70pF for VREFA/B). VOUTA, VOUTB,
VOUTC, and VOUTD can be represented by a digitally
programmable voltage source as:
VOUT = Nb x VREF / 256
where Nb is the numeric value of the DAC’s binary
input code.
Output Buffer Amplifiers
All voltage outputs are internally buffered by precision
unity-gain followers, which slew at greater than 3V/µs.
When driving 2kΩ in parallel with 100pF with a full-scale
transition (0V to +10V or +10V to 0V), the output settles
to ±1/2LSB in less than 4µs. The buffers will also drive
2kΩ in parallel with 500pF to 10V levels without oscilla-
tion. Typical dynamic response and settling perfor-
mance of the MAX500 is shown in Figures 2 and 3.
A simplified circuit diagram of an output buffer is
shown in Figure 4. Input common-mode range to
AGND is provided by a PMOS input structure. The out-
put circuitry incorporates a pull-down circuit to actively
drive VOUT to within +15mV of the negative supply
(VSS). The buffer circuitry allows each DAC output to
_______________________________________________________________________________________ 5
5 Page 
CMOS, Quad, Serial-Interface
8-Bit DAC
Using an AC Reference
In applications where VREF has AC signal components,
the MAX500 has multiplying capability within the limits
of the VREF input range specifications. Figure 11 shows
a technique for applying a sine-wave signal to the refer-
ence input, where the AC signal is biased up before
being applied to VREF. Output distortion is typically less
than 0.1% with input frequencies up to 50kHz, and the
typical -3dB frequency is 700kHz. Note that VREF must
never be more negative than AGND.
Generating VSS
The performance of the MAX500 is specified for both
dual and single-supply (VSS = 0V) operation. When the
improved performance of dual-supply operation is
desired, but only a single supply is available, a -5V VSS
supply can be generated using an ICL7660 in one of
the circuits of Figure 12.
Digital Interface Applications
Figures 13 through 16 show examples of interfacing the
MAX500 to most popular microprocessors.
+15V
15k
AC
REFERENCE
INPUT
+4V
-4V
10k
4
VREFA/B
DAC B
VSS
3
-5V (OR GND)
AGND
5
DIGITAL INPUTS NOT SHOWN
Figure 11. AC Reference Input Circuit
14
VDD
VOUTB 1 VOUTB
MAX500
DGND
6
12V to 15V
10k
2N2222
6V
ZENER
10k 10µF
10µF
2
CAP+
8
V+
4
CAP-
3
ICL7660
GND
VOUT
5
+5V
LOGIC
SUPPLY
-5V
VSS OUT
10µF
10µF
2
CAP+
8
V+
4
CAP-
3
ICL7660
GND
VOUT
5
-5V
VSS OUT
10µF
Figure 12. Generating -5V for VSS
80C51
P1.0
P1.1
P1.2
P1.3 . . . . . . .
MAX500
SCL SRO
SDA
LDAC
LOAD*
VOUTA
VOUTB
VOUTC
VOUTD
VREFA/B
VREFC
VREFD
A15
A0
Z80
I/O REQ
WR
INT
D7
D0
ADDRESS BUS
EN
ADDRESS
CODE
A1 A0 B/A Z8420
C/D B0
SCL MAX500
CE B1
SDA
RD
B2 LDAC
INT
D7 B3 . . LOAD*
D0
DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 13. 80C51 Interface
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR
CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 14. Z-80 with Z8420 PIO Interface
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX500.PDF ] | |
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