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M41ST84W Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer M41ST84W
Beschreibung 5.0 or 3.0V / 512 bit 64 x 8 SERIAL RTC with SUPERVISORY FUNCTIONS
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 31 Seiten
M41ST84W Datasheet, Funktion
M41ST84Y
M41ST84W
5.0 or 3.0V, 512 bit (64 x 8) SERIAL RTC
with SUPERVISORY FUNCTIONS
FEATURES SUMMARY
s 5.0 OR 3.0V OPERATING VOLTAGE
s SERIAL INTERFACE SUPPORTS I2C BUS
(400 KHz)
s OPTIMIZED FOR MINIMAL INTERCONNECT
TO MCU
s 2.5 TO 5.5V OSCILLATOR OPERATING
VOLTAGE
s AUTOMATIC SWITCH-OVER and DESELECT
CIRCUITRY
s CHOICE OF POWER-FAIL DESELECT
VOLTAGES:
– M41ST84Y: VCC = 4.5 to 5.5V;
4.20V VPFD 4.50V
– M41ST84W: VCC = 2.7 to 3.6V;
2.55V VPFD 2.70V
s 1.25V REFERENCE (for PFI/PFO)
s COUNTERS FOR TENTHS/HUNDREDTHS
OF SECONDS, SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEAR, and
CENTURY
s 44 BYTES OF GENERAL PURPOSE RAM
s PROGRAMMABLE ALARM and INTERRUPT
FUNCTION (VALID EVEN DURING BATTERY
BACK-UP MODE)
s WATCHDOG TIMER
s MICROPROCESSOR POWER-ON RESET
s BATTERY LOW FLAG
s ULTRA-LOW BATTERY SUPPLY CURRENT
OF 500 nA (max)
s OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT® TOP (to be
ordered separately)
s SNAPHAT PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP,
WHICH CONTAINS THE BATTERY and
CRYSTAL
* Contact Local Sales Office
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package*
SNAPHAT (SH)
Battery & Crystal
28
1
SOH28 (MH)
June 2003
Rev. 4.0
1/31






M41ST84W Datasheet, Funktion
M41ST84Y, M41ST84W
Figure 7. Hardware Hookup
Unregulated
Voltage
Regulator
VIN VCC
M41ST84Y/W
VCC
IRQ/FT/OUT
To INT
SCL
WDI
RSTIN
SDA
RST
SQW
To RST
To LED Display
R1
PFI
R2
VSS
PFO
To NMI
AI03680
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TSTG
Storage Temperature (VCC Off, Oscillator Off)
SNAPHAT®
SOIC
–40 to 85
–55 to 125
°C
°C
TSLD (1) Lead Solder Temperature for 10 seconds
260 °C
VIO Input or Output Voltages
–0.3 to VCC + 0.3
V
VCC Supply Voltage
M41ST84Y
M41ST84W
–0.3 to 7.0
–0.3 to 4.6
V
V
IO Output Current
20 mA
PD Power Dissipation
1W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
6/31

6 Page









M41ST84W pdf, datenblatt
M41ST84Y, M41ST84W
READ Mode
In this mode the master reads the M41ST84Y/W
slave after setting the slave address (see Figure
12, page 12). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address ‘An’ is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an Acknowledge Bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41ST84Y/W slave transmitter will
now place the data byte at address An+1 on the
bus, the master receiver reads and acknowledges
the new byte and the address pointer is
incremented to “An+2.”
Figure 12. Slave Address Location
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 13,
page 12).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41ST84Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 14, page 13).
R/W
START
SLAVE ADDRESS
A
11 0100 0
Figure 13. READ Mode Sequence
AI00602
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
S
DATA n
DATA n+1
BUS ACTIVITY:
SLAVE
ADDRESS
SLAVE
ADDRESS
12/31
DATA n+X P
AI00899

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