|
|
PDF MH8S64AQFC-8L Data sheet ( Hoja de datos )
| Número de pieza | MH8S64AQFC-8L | |
| Descripción | 536 /870 /912-BIT (8 /388 /608 - WORD BY 64-BIT)SynchronousDRAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MH8S64AQFC-8L (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64AQFC is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of four
industry standard 8Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
-6,-6L
-7,-7L
-8,-8L
Frequency
CLK Access Time
(Component SDRAM)
133MHz
5.4ns(CL=3)
100MHz
6.0ns(CL=2)
100MHz
6.0ns(CL=3)
Utilizes industry standard 8M x 16 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
MIT-DS-0374-0.3
MITSUBISHI
ELECTRIC
( 1 / 55 )
143
144
22.Sep.2000
1 page  
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table II
31 Density of each bank on module
-6,-6L
32 Command and Address signal input setup time
-7,-7L,-8,-8L
-6,-6L
33 Command and Address signal input hold time
-7,-7L,-8,-8L
34 Data signal input setup time
-6,-6L
-7,-7L,-8,-8L
35 Data signal input hold time
-6,-6L
-7,-7L,-8,-8L
36-61
62
Superset Information (may be used in future)
SPD Revision
63 Checksum for bytes 0-62
64-71
Manufactures Jedec ID code per JEP-108E
72 Manufacturing location
73-90
Manufactures Part Number
91-92
93-94
95-98
99-125
126
127
128+
Revision Code
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
Intetl specification frequency
Intel specification CAS# Latency support
Unused storage locations
-6,-6L,-7,7L
-8,8L
64MByte
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
option
rev 1.2B
Check sum for -6,-6L
Check sum for -7,-7L
Check sum for -8,-8L
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
Germany
MH8S64AQFC-6
MH8S64AQFC-6L
MH8S64AQFC-7
MH8S64AQFC-7L
MH8S64AQFC-8
MH8S64AQFC-8L
PCB revision
year/week code
serial number
option
100MHz
CL=2/3,AP,CK0,1
CL=3,AP,CK0,1
open
10
15
20
08
10
15
20
08
10
00
12
AC
0D
4D
1CFFFFFFFFFFFFFF
01
02
03
04
4D4838533634415146432D36202020202020
4D4838533634415146432D364C2020202020
4D4838533634415146432D37202020202020
4D4838533634415146432D374C2020202020
4D4838533634415146432D38202020202020
4D4838533634415146432D384C2020202020
rrrr
yyww
ssssssss
00
64
8F
8D
00
MIT-DS-0374-0.3
MITSUBISHI
ELECTRIC
( 5 / 55 )
22.Sep.2000
5 Page 
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64AQFC -6,-6L,-7,-7L,-8,-8L
536,870,912-BIT (8,388,608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State
PRE -
CHARGING
ROW
ACT IVATING
WRITE RE-
COVERING
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Idle after tRP)
L H H HX
NOP
NOP(Idle after tRP)
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA NOP*4(Idle after tRP)
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Row Active after tRCD
L H H HX
NOP
NOP(Row Active after tRCD
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP
L H H HX
NOP
NOP
L H H L BA
TBST
ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA
ACT ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0374-0.3
MITSUBISHI
ELECTRIC
( 11 / 55 )
22.Sep.2000
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH8S64AQFC-8L.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MH8S64AQFC-8 | 536 /870 /912-BIT (8 /388 /608 - WORD BY 64-BIT)SynchronousDRAM | Mitsubishi |
| MH8S64AQFC-8 | 536 /870 /912-BIT (8 /388 /608 - WORD BY 64-BIT)SynchronousDRAM | Mitsubishi |
| MH8S64AQFC-8L | 536 /870 /912-BIT (8 /388 /608 - WORD BY 64-BIT)SynchronousDRAM | Mitsubishi |
| MH8S64AQFC-8L | 536 /870 /912-BIT (8 /388 /608 - WORD BY 64-BIT)SynchronousDRAM | Mitsubishi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |