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MH16V725BATJ-6 Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer MH16V725BATJ-6
Beschreibung HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 22 Seiten
MH16V725BATJ-6 Datasheet, Funktion
Preliminary Spec.
MITSUBISHI LSIs
MH16V725BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V725BATJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard 16M
x 4 dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
MH16V725BATJ-5
MH16V725BATJ-6
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
50 18 30 18 84 5.50
60 20 35 20 104 4.60
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . 121mW(Max)
Low operation power dissipation
MH16V725BATJ -5 . . . . . . . . . . . . . . . . . 6.58W(Max)
MH16V725BATJ -6 . . . . . . . . . . . . . . . . . 5.94W(Max)
All input,output LVTTL compatible
Includes(0.22uF x 20) decoupling capacitors
4096 refresh cycle every 64ms (A0~A12)
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
-5 1 1 1 1 1 0 0 0 0 0
-6 1 1 1 1 1 1 1 0 0 0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
MIT-DS-0271-0.0
MITSUBISHI
ELECTRIC
( 1 / 22 )
168pin 84pin
Oct.1.1998






MH16V725BATJ-6 Datasheet, Funktion
Preliminary Spec.
MITSUBISHI LSIs
MH16V725BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Symbol
Parameter
Limits
-5 -6
Unit
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from /CAS
Access time from /RAS
Columu address access time
Access time from /CAS precharge
Access time from /OE
Output hold time /CAS high
Output hold time /RAS high
Output low impedance time from /CAS low
Output disable time after /OE high
Output disable time after /WE high
Output disable time after /CAS high
Output disable time after /RAS high
Min Max Min Max
(Note 7,8)
18
20
(Note 7,9)
50
60
(Note 7,10)
30
35
(Note 7,11)
33
38
(Note 7)
18
20
10 10
(Note 13) 5
5
(Note 7) 10
10
(Note 12)
18
20
(Note 12)
18
20
(Note 12,13)
18
20
(Note 12,13)
13
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS-Only refresh or /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1TTL loads and 50pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V (VOH) and 0.8V (VOL).
8: Assumes that tRCDtRCD(max), tASCtASC(max) and tCPtCP(max).
9: Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRADtRAD(max) and tASCtASC(max).
11: Assumes that tCPtCP(max) and tASCtASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state
(IOUTI+/-10uAI) and is not reference to VOH(min) or VOL(max).
13: Output is disable after both /RAS and /CAS go to high
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Symbol
Parameter
tREF
tRP
tRCD
tCRP
tRPC
tCPN
tRAD
tASR
tASC
tRAH
tCAH
tDZC
tDZO
tRDD
tCDD
tODD
tT
Refresh cycle time
/RAS high pulse width
Delay time, /RAS low to /CAS low
Delay time, /CAS high to /RAS low
Delay time, /RAS high to /CAS low
/CAS high pulse width
Column address delay time from /RAS low
Row address setup time before /RAS low
Column address setup time before /CAS low
Row address hold time after /RAS low
Column address hold time after /CAS low
Delay time, data to /CAS low
Delay time, data to /OE low
Delay time, /RAS high to data
Delay time, /CAS high to data
Delay time, /OE high to data
Transition time
(Note16)
(Note17)
(Note18)
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
(Note21)
Limits
-5 -6
Min Max Min Max
64 64
30 40
9 32
9 40
10 10
00
8 10
5 20 7 25
55
0 10 0 13
35
8 10
00
00
13 15
18 20
18 20
1 50 1 50
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by
tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
MIT-DS-0271-0.0
MITSUBISHI
ELECTRIC
( 6 / 22 )
Oct.1.1998

6 Page









MH16V725BATJ-6 pdf, datenblatt
Preliminary Spec.
MITSUBISHI LSIs
MH16V725BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
/RAS
VIH
VIL
/CAS
VIH
VIL
A0~A12,B0
VIH
VIL
VIH
/W
VIL
DQ
(INPUTS)
VIH
VIL
DQ
(OUTPUTS)
VOH
VOL
VIH
/OE
VIL
tRWC
tRAS
tRP
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tRCS
tCAH
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tCRP
tCWL
tRWL
tWP
tASR
ROW
ADDRESS
tDZC
Hi-Z
tCAC
tAA
tCLZ
tDS tDH
DATA VALID
Hi-Z
tRAC
tDZO
DATA
VALID
tOEA
tODD
tOEZ
tOEH
Hi-Z
MIT-DS-0271-0.0
MITSUBISHI
ELECTRIC
( 12 / 22 )
Oct.1.1998

12 Page





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