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MH16V7245BWJ-6 Schematic ( PDF Datasheet ) - Mitsubishi

Teilenummer MH16V7245BWJ-6
Beschreibung HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hersteller Mitsubishi
Logo Mitsubishi Logo 




Gesamt 22 Seiten
MH16V7245BWJ-6 Datasheet, Funktion
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V7245BWJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard
16M x 4 dynamic RAMs in SOJ and one industry standard
EEPROM in TSSOP.
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH16V7245BWJ-5 50 13 25 13 84 7.02
MH16V7245BWJ-6 60 15 30 15 104 5.85
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
32.4mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH16V7245BWJ -5 . . . . . . . . . . . . . . . . . . 8.43W(Max)
MH16V7245BWJ -6 . . . . . . . . . . . . . . . . . . 7.78W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 18) decoupling capacitors
4096 refresh cycle every 64ms
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address A0 ~ A11
Column Address A0 ~ A11
APPLICATION
Main memory unit for computers , Microcomputer memory
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
168pin 84pin
MIT-DS-0241-0.0
MITSUBISHI
ELECTRIC
( 1 / 22 )
28/Jul/`98






MH16V7245BWJ-6 Datasheet, Funktion
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)
Symbol
Parameter
Limits
-5 -6
Unit
Min Max
Min Max
tCAC Access time from /CAS
(Note 7,8)
13
15 ns
tRAC Access time from /RAS
(Note 7,9)
50
60 ns
tAA Column address access time
(Note 7,10)
25
30 ns
tCPA Access time from /CAS precharge
(Note 7,11)
28
33 ns
tOEA Access time from /OE
(Note 7)
13
15 ns
tOHC Output hold time from /CAS
5 5 ns
tOHR
tCLZ
tOEZ
Output hold time from /RAS
Output low impedance time /CAS low
Output disable time after /OE high
(Note 13)
(Note 7)
(Note 12)
5
5
13
5 ns
5 ns
15 ns
tWEZ
tOFF
Output disable time after /WE high
Output disable time after /CAS high
(Note 12)
(Note 12,13)
13
13
15 ns
15 ns
tREZ
Output disable time after /RAS high
(Note 12,13)
13
15 ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD tRCD(max), tASC tASC(max) and tCP tCP(max).
9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD tRAD(max) and tASC tASC(max).
11: Assumes that tCP tCP(max) and tASC tASC(max).
12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT I ± 10uA I )
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both /RAS and /CAS go to high.
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)
Symbol
Parameter
-5
Min
Limits
-6
Max Min
Max
Unit
tREF Refresh cycle time
64 64 ms
tRP /RAS high pulse width
30 40 ns
tRCD Delay time, /RAS low to /CAS low
(Note16)
14
37
14
45
ns
tCRP Delay time, /CAS high to /RAS low
5 5 ns
tRPC Delay time, /RAS high to /CAS low
0 0 ns
tCPN /CAS high pulse width
8 10 ns
tRAD Column address delay time from /RAS low (Note17) 10 25 12 30 ns
tASR Row address setup time before /RAS low
0
0 ns
tASC Column address setup time before /CAS low(Note18)
0
10
0 13 ns
tRAH Row address hold time after /RAS low
8
10
ns
tCAH Column address hold time after /CAS low
8
10
ns
tDZC Delay time, data to /CAS low
(Note19)
0
0 ns
tDZO Delay time, data to /OE low
(Note19)
0
0 ns
tRDD Delay time, /RAS high to data
(Note20)
13
15
ns
tCDD Delay time, /CAS high to data
(Note20)
13
15
ns
tODD Delay time, /OE high to data
(Note20)
13
15
ns
tT Transition time
(Note21)
1
50
1 50 ns
Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA.
18: tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC.
19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).
MIT-DS-0241-0.0
MITSUBISHI
ELECTRIC
( 6 / 22 )
28/Jul/`98

6 Page









MH16V7245BWJ-6 pdf, datenblatt
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V7245BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
/RAS
VIH
VIL
/CAS
VIH
VIL
Address
VIH
VIL
VIH
/W
VIL
DQ
(INPUTS)
VIH
VIL
DQ
(OUTPUTS)
VOH
VOL
VIH
/OE
VIL
tRWC
tRAS
tRP
tCRP
tRCD
tCSH
tRSH
tCAS
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tRCS
tCAH
COLUMN
ADDRESS
tAWD
tCWD
tRWD
tCWL
tRWL
tWP
tCRP
tASR
ROW
ADDRESS
tDZC
Hi-Z
tCAC
tAA
tCLZ
tDS
Hi-Z
tRAC
tDZO
DATA
VALID
tOEA
tODD
tOEZ
tDH
DATA VALID
tOEH
Hi-Z
MIT-DS-0241-0.0
MITSUBISHI
ELECTRIC
( 12 / 22 )
28/Jul/`98

12 Page





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