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PDF MH16V7245BATJ-5 Data sheet ( Hoja de datos )
| Número de pieza | MH16V7245BATJ-5 | |
| Descripción | HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V7245BATJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard 16M
x 4 dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH16V7245BATJ-5 50 18 30 18 84 7.12
MH16V7245BATJ-6 60 20 35 20 104 5.95
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual in-line pacege)
Single 3.3V(+/-0.3V) supply operation
Low stand-by power dissipation . . . . . . . . 121mW(Max)
Low operation power dissipation
MH16V7245BATJ -5 . . . . . . . . . . . . . . . . . 8.53W(Max)
MH16V7245BATJ -6 . . . . . . . . . . . . . . . . . 7.88W(Max)
All input,output LVTTL compatible
Includes(0.22uF x 20) decoupling capacitors
4096 refresh cycle every 64ms (A0~A11)
JEDEC standard pin configration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
APPLICATION
Main memory unit for computers , Microcomputer memory
PD&ID TABLE
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0 ID1
-5 1 1 1 1 1 0 0 0 0 0
-6 1 1 1 1 1 1 1 0 0 0
1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 1 / 23 )
168pin 84pin
5/Nov./1998
1 page  
Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Vcc Supply voltage
VI Input voltage
VO Output voltage
IO Output current
Pd Power dissipation
Topr
Operating temperature
Tstg Storage temperature
Conditions
With respect to Vss
Ta=25°C
Ratings
-0.5~4.6
-0.5~ 4.6
-0.5~ 4.6
50
21.6
0~70
-40~100
Unit
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C, unless otherwise noted) (Note 1)
Symbol
Parameter
Limits
Min Nom Max
Unit
Vcc Supply voltage
3.0 3.3 3.6
V
Vss Supply voltage
0 0 0V
VIH High-level input voltage, all inputs 2.0
Vcc+0.3 V
VIL Low-level input voltage
-0.3 0.8 V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted) (Note 2)
Symbol
Parameter
VOH
High-level output voltage
VOL
Low-level output voltage
IOZ Off-state output current
I I Input current (except /RAS)
I I (RAS) Input current (/RAS)
Average supply
ICC1 (AV) current
from Vcc operating (Note 3,4,5)
-5
-6
ICC2
Supply current from Vcc , stand-by
Average supply current
ICC4(AV) from Vcc
Hyper-Page-Mode (Note 3,4,5)
Average supply current from Vcc
ICC6(AV) /CAS before /RAS refresh mode
(Note 3)
-5
-6
-5
-6
Test conditions
Limits
Min Typ Max
IOH=-2mA
IOL=2mA
Q floating 0V≤VOUT≤Vcc
0V≤VIN≤Vcc+0.3, Other input pins=0V
0V≤VIN≤Vcc+0.3, Other input pins=0V
2.4
0
-10
-10
-90
Vcc
0.4
10
10
90
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS=/WE ≥Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
2360
2180
38
29
1820
1640
/CAS before /RAS refresh cycling
tRC=min.
output open
2360
2180
Unit
V
V
uA
uA
uA
mA
mA
mA
mA
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of colmun address being changed once or less while /RAS=VIL and /CAS=VIH
CAPACITANCE (Ta = 0~70°C, Vcc = 3.3V+/-0.3V, Vss = 0V, unless otherwise noted)
Symbol
Parameter
CI (/RAS) Input capacitance, /RAS input
CI Input capacitance, except /RAS input
C(DQ) Input/Output capacitance,DATA
Test conditions
VI=Vss
f=1MHZ
Vi=25mVrms
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 5 / 23 )
Limits
Min Typ Max
80
15
18
Unit
pF
pF
pF
5/Nov./1998
5 Page 
Preliminary Spec.
MITSUBISHI LSIs
MH16V7245BATJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Delayed Write Cycle
/RAS
VIH
VIL
/CAS
VIH
VIL
A0~A11,B0
VIH
VIL
VIH
/W
VIL
DQ
(INPUTS)
VIH
VIL
DQ
(OUTPUTS)
VOH
VOL
VIH
/OE
VIL
tWC
tRAS
tRP
tCRP
tRCD
tCSH
tRSH
tCAS
tCRP
tASR
tRAH
ROW
ADDRESS
tASC
tRCS
tCAH
COLUMN
ADDRESS
tCWL
tRWL
tWP
tDZC
Hi-Z
tCLZ
tWCH
tDS tDH
DATA
VALID
tASR
ROW
ADDRESS
Hi-Z
tDZO
tOEZ
tODD
tOEH
Hi-Z
MIT-DS-0277-0.0
MITSUBISHI
ELECTRIC
( 11 / 23 )
5/Nov./1998
11 Page | ||
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| PDF Descargar | [ Datasheet MH16V7245BATJ-5.PDF ] | |
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